代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
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www.eeworm.com/read/347114/11693581
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_ram_clear is
port(
aclr : in vl_logic;
d : in vl_logic;
q : out
www.eeworm.com/read/347114/11693674
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity b17mux21 is
port(
\MO\ : out vl_logic_vector(16 downto 0);
\A\ : in vl_logic_vector(16 downto 0);
www.eeworm.com/read/347114/11693681
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_jtag is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_
www.eeworm.com/read/347114/11693710
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_lcell is
generic(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mo
www.eeworm.com/read/347114/11694491
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity \CLKLOCK\ is
generic(
\CLOCKBOOST\ : integer := 1;
\INPUT_FREQUENCY\: real := 50.000000;
\TPD\ : integer :
www.eeworm.com/read/347114/11699250
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_ram_clear is
port(
aclr : in vl_logic;
d : in vl_logic;
q : out
www.eeworm.com/read/347114/11699328
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(15 downto 0);
\A\ : in vl_logic_vector(15 downto 0);
www.eeworm.com/read/347114/11699414
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_lcell is
generic(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mo
www.eeworm.com/read/347114/11699431
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_jtag is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_
www.eeworm.com/read/347114/11699503
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity b17mux21 is
port(
\MO\ : out vl_logic_vector(16 downto 0);
\A\ : in vl_logic_vector(16 downto 0);