代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
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www.eeworm.com/read/478173/6720985
out 30_preproc_nows.out
verilog/inc_ifdef.v:1: `line 1 "verilog/inc1.v" 1
verilog/inc_ifdef.v:1: `line 1 "verilog/inc1.v" 0
verilog/inc_ifdef.v:1: `line 1 "verilog/inc2.v" 1
verilog/inc_ifdef.v:1: `line 1 "verilog/inc2.v" 0
www.eeworm.com/read/478173/6720998
out 35_sigparser.out
verilog/v_hier_subprim.v:008: MODULE 'primitive' 'v_hier_prim' undef '0'
verilog/v_hier_subprim.v:010: PORT 'q'
verilog/v_hier_subprim.v:012: PORT 'a'
verilog/v_hier_subprim.v:014: SIGNAL_DECL 'ou
www.eeworm.com/read/410692/11271913
hif clock.hif
Version 7.2 Build 151 09/26/2007 SJ Full Version
39
2304
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Pat
www.eeworm.com/read/410651/11273319
qmsg ps2.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/410306/11293879
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity rom is
port(
data : out vl_logic_vector(7 downto 0);
addr : in vl_logic_vector(12 downto 0);
www.eeworm.com/read/410306/11293884
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity alu is
generic(
HLT : integer := 0;
SKZ : integer := 1;
ADD : integer := 2;
\A
www.eeworm.com/read/410306/11293916
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram is
port(
data : inout vl_logic_vector(7 downto 0);
addr : in vl_logic_vector(9 downto 0);
e
www.eeworm.com/read/410306/11293921
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity accum is
port(
accum : out vl_logic_vector(7 downto 0);
data : in vl_logic_vector(7 downto 0);
www.eeworm.com/read/409880/11308422
txt run_options.txt
#-- Synplicity, Inc.
#-- Version 9.4A1
#-- Project file D:\Actelprj\LCD_1602\synthesis\run_options.txt
#-- Written on Thu Jan 29 17:10:47 2009
#add_file options
add_file -verilog "D:/Actelprj
www.eeworm.com/read/409533/11320334
sty i2c_sl~2.sty
[Normal]
synlibXRef=lc4k_vlg, Verilog.TASKLSVlog, 0, Yes
_vlog_std_v2001=lc4k_vlg, Verilog.TASKLSVlog, 0, True
[STRATEGY-LIST]
Normal=True, 1125078904
[TOUCHED-REPORT]
Design.bl2File=1125087229