代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/468753/6987380
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity decoder is
port(
\in\ : in vl_logic_vector(31 downto 0);
sel : in vl_logic;
o0
www.eeworm.com/read/468753/6987386
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bitwise_xor is
port(
in1 : in vl_logic_vector(31 downto 0);
in2 : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/468753/6987406
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux2 is
port(
i0 : in vl_logic_vector(31 downto 0);
i1 : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/468753/6987421
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux6_1 is
port(
in2 : in vl_logic;
in3 : in vl_logic;
in4 : in vl_logic;
www.eeworm.com/read/468753/6987428
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux4 is
port(
i0 : in vl_logic_vector(31 downto 0);
i1 : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/468753/6987437
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity csa is
port(
A : in vl_logic_vector(31 downto 0);
B : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/468753/6987451
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity arm7 is
port(
nOPC : out vl_logic;
nCPI : out vl_logic;
CPA : in vl_logic;
www.eeworm.com/read/468753/6987457
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity sum6 is
port(
s : out vl_logic_vector(5 downto 0);
p : in vl_logic_vector(5 downto 0);
www.eeworm.com/read/468753/6987461
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity add4 is
port(
\in\ : in vl_logic_vector(31 downto 0);
\out\ : out vl_logic_vector(31 downto 0)
);
www.eeworm.com/read/468753/6987465
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity sub4 is
port(
\in\ : in vl_logic_vector(31 downto 0);
\out\ : out vl_logic_vector(31 downto 0)
);