_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity mux6_1 is
    port(
        in2             : in     vl_logic;
        in3             : in     vl_logic;
        in4             : in     vl_logic;
        in5             : in     vl_logic;
        in6             : in     vl_logic;
        in7             : in     vl_logic;
        sel             : in     vl_logic_vector(4 downto 0);
        \out\           : out    vl_logic
    );
end mux6_1;