_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity csa is
    port(
        A               : in     vl_logic_vector(31 downto 0);
        B               : in     vl_logic_vector(31 downto 0);
        Cin             : in     vl_logic;
        Cout            : out    vl_logic;
        Overflow        : out    vl_logic;
        Sum             : out    vl_logic_vector(31 downto 0)
    );
end csa;