代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/468753/6987087
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity sum7 is
port(
s : out vl_logic_vector(6 downto 0);
p : in vl_logic_vector(6 downto 0);
www.eeworm.com/read/468753/6987112
vopta5rsb4
library verilog;
use verilog.vl_types.all;
entity sub4 is
port(
\in\ : in vl_logic_vector(31 downto 0);
\out\ : out vl_logic_vector(31 downto 0)
);
www.eeworm.com/read/468753/6987113
voptxhkq55
library verilog;
use verilog.vl_types.all;
entity decoder is
port(
\in\ : in vl_logic_vector(31 downto 0);
sel : in vl_logic;
o0
www.eeworm.com/read/468753/6987139
voptn3041v
library verilog;
use verilog.vl_types.all;
entity add4 is
port(
\in\ : in vl_logic_vector(31 downto 0);
\out\ : out vl_logic_vector(31 downto 0)
);
www.eeworm.com/read/468753/6987152
vopt7cadfc
library verilog;
use verilog.vl_types.all;
entity mux8 is
port(
i0 : in vl_logic_vector(31 downto 0);
i1 : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/468753/6987164
voptcfgm13
library verilog;
use verilog.vl_types.all;
entity mux2 is
port(
i0 : in vl_logic_vector(31 downto 0);
i1 : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/468753/6987183
voptkwfa9r
library verilog;
use verilog.vl_types.all;
entity arm7 is
port(
nOPC : out vl_logic;
nCPI : out vl_logic;
CPA : in vl_logic;
www.eeworm.com/read/468753/6987188
vopt09tmbf
library verilog;
use verilog.vl_types.all;
entity mux4 is
port(
i0 : in vl_logic_vector(31 downto 0);
i1 : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/468753/6987190
voptryfdn8
library verilog;
use verilog.vl_types.all;
entity mux24 is
port(
i0 : in vl_logic_vector(3 downto 0);
i1 : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/468753/6987194
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux8 is
port(
i0 : in vl_logic_vector(31 downto 0);
i1 : in vl_logic_vector(31 downto 0);