代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585259
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvdci_18 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_
www.eeworm.com/read/159314/5585261
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15_s_8 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585272
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_f_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
www.eeworm.com/read/159314/5585282
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnn_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585283
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxf7_d is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
lo
www.eeworm.com/read/159314/5585300
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity startup is
generic(
cds_action : string := "ignore"
);
port(
donein : out vl_logic;
q1q4
www.eeworm.com/read/159314/5585301
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut2 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i0 : in
www.eeworm.com/read/159314/5585303
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and3 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585305
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdpe_1 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
www.eeworm.com/read/159314/5585307
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnn_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic