_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity startup is
    generic(
        cds_action      : string  := "ignore"
    );
    port(
        donein          : out    vl_logic;
        q1q4            : out    vl_logic;
        q2              : out    vl_logic;
        q3              : out    vl_logic;
        clk             : in     vl_logic;
        gsr             : in     vl_logic;
        gts             : in     vl_logic
    );
end startup;