_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity lut2 is
    generic(
        init            : integer := 0
    );
    port(
        o               : out    vl_logic;
        i0              : in     vl_logic;
        i1              : in     vl_logic
    );
end lut2;