代码搜索：verilog hdl 是什么？

找到约 10,000 项符合「verilog hdl 是什么？」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/364280/9914208

qsf ps2.qsf

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
·
www.eeworm.com/read/364280/9914262

qmsg ps2.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
·
www.eeworm.com/read/364280/9914381

qmsg lcd_1602.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
·
www.eeworm.com/read/364280/9914709

qmsg beep.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
·
www.eeworm.com/read/364280/9915101

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity mult16S is port( P : out vl_logic_vector(31 downto 0); A : in vl_logic_vector(15 downto 0);
·
www.eeworm.com/read/362402/10000554

qmsg lcd_v.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
·
www.eeworm.com/read/361328/10057814

qmsg gate_control.tan.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
·
www.eeworm.com/read/359174/10162684

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity clk is port( clk : in vl_logic; rst : in vl_logic; clk1 : out vl_logic )
·
www.eeworm.com/read/358544/10185645

gfl cpld.gfl

# Verilog : PDCL (jhdparse) __projnav/TOP_jhdparse_tcl.rsp # Implmentation : Lock Pins (CPLD flow) __projnav/top_TO_lc_tcl.rsp top._lc last_used.ngd top.cmd_log # xst flow : RunXST top.syr to
·
www.eeworm.com/read/281017/10272381

qmsg eeprom.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
·