_primary.vhd

来自「Verilog 经典实例」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity mult16S is
    port(
        P               : out    vl_logic_vector(31 downto 0);
        A               : in     vl_logic_vector(15 downto 0);
        B               : in     vl_logic_vector(15 downto 0)
    );
end mult16S;