代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/314066/13575713
_prj tx2bit._prj
insert `timescale 1ns/1ns
include
include ../6-1/m2_1.v ../6-1/ddrfd.v ../6-1/load_gen.v ../6-1/piso.v ../6-1/tx2bit.v
include D:/Xilinx/verilog/src/iSE/unisim_comp.v
www.eeworm.com/read/313799/13580640
rpt main.map.rpt
Analysis & Synthesis report for main
Mon Jul 17 23:30:02 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal No
www.eeworm.com/read/313799/13580665
qmsg main.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
www.eeworm.com/read/309977/13661129
qmsg zz.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/309739/13665087
cfg compxlib.cfg
#*****************************************************************
# compxlib initialization file (compxlib.cfg) *
#
www.eeworm.com/read/308751/13693485
versim_xlate armtst.versim_xlate
armtst.versim_xlate -- generated only for ProjNav status tracking
Simulation Model Target: Generic_Verilog
www.eeworm.com/read/306604/13741319
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity test is
generic(
period : integer := 200;
duty_cycle : real := 0.500000;
offset : integer := 0
www.eeworm.com/read/151353/5683665
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity global is
port(
\out\ : out vl_logic
);
end global;
www.eeworm.com/read/146593/5736618
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity m3s005br is
port(
clk : in vl_logic;
nrst : in vl_logic;
a : in vl_logic_
www.eeworm.com/read/146593/5736625
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity m3s006br is
port(
clk : in vl_logic;
nrst : in vl_logic;
clkenab : in vl_logic;