zz.map.qmsg

基于FPGA的交通灯系统控制程序。用的是verilog.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 22 16:56:26 2001 " "Info: Processing started: Sat Sep 22 16:56:26 2001" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off zz -c zz " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off zz -c zz" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_PREVIOUSLY_DECLARED_WITHOUT_RANGE" "LAMPA traffic.v(9) " "Warning (10226): Verilog HDL Multiple Declaration warning at traffic.v(9): net, port, or variable \"LAMPA\" was previously declared without a range" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 9 0 0 } }  } 0 10226 "Verilog HDL Multiple Declaration warning at %2!s!: net, port, or variable \"%1!s!\" was previously declared without a range" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "LAMPA traffic.v(3) " "Info (10151): Verilog HDL Declaration information at traffic.v(3): \"LAMPA\" is declared here" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 3 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Warning" "WVRFX_VERI_PREVIOUSLY_DECLARED_WITHOUT_RANGE" "LAMPB traffic.v(9) " "Warning (10226): Verilog HDL Multiple Declaration warning at traffic.v(9): net, port, or variable \"LAMPB\" was previously declared without a range" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 9 0 0 } }  } 0 10226 "Verilog HDL Multiple Declaration warning at %2!s!: net, port, or variable \"%1!s!\" was previously declared without a range" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "LAMPB traffic.v(3) " "Info (10151): Verilog HDL Declaration information at traffic.v(3): \"LAMPB\" is declared here" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 3 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "traffic.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file traffic.v" { { "Info" "ISGN_ENTITY_NAME" "1 traffic " "Info: Found entity 1: traffic" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "zz.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file zz.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 zz " "Info: Found entity 1: zz" {  } { { "zz.bdf" "" { Schematic "D:/traffic light/zz.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "zz " "Info: Elaborating entity \"zz\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "traffic traffic:inst " "Info: Elaborating entity \"traffic\" for hierarchy \"traffic:inst\"" {  } { { "zz.bdf" "inst" { Schematic "D:/traffic light/zz.bdf" { { 104 184 328 232 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "ared traffic.v(11) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable \"ared\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 11 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ared\[7\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ared\[7\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ared\[6\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ared\[6\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ared\[5\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ared\[5\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ared\[4\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ared\[4\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ared\[3\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ared\[3\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ared\[2\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ared\[2\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ared\[1\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ared\[1\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ared\[0\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ared\[0\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "ayellow traffic.v(11) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable \"ayellow\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 11 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ayellow\[7\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ayellow\[7\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ayellow\[6\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ayellow\[6\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ayellow\[5\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ayellow\[5\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ayellow\[4\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ayellow\[4\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ayellow\[3\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ayellow\[3\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ayellow\[2\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ayellow\[2\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ayellow\[1\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ayellow\[1\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ayellow\[0\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"ayellow\[0\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "agreen traffic.v(11) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable \"agreen\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 11 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "agreen\[7\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"agreen\[7\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "agreen\[6\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"agreen\[6\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "agreen\[5\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"agreen\[5\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "agreen\[4\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"agreen\[4\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}