代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/321790/13398818
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_asynch_lcell is
generic(
operation_mode : string := "normal";
sum_lutc_input : string := "datac";
lut_mask
www.eeworm.com/read/321790/13398932
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and1 is
port(
y : out vl_logic;
in1 : in vl_logic
);
end and1;
www.eeworm.com/read/321790/13398947
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity prim_dffe is
// This module cannot be connected to from
// VHDL because it has unnamed ports.
end prim_dffe;
www.eeworm.com/read/321790/13398971
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_asynch_lcell is
generic(
operation_mode : string := "normal";
sum_lutc_input : string := "datac";
lut_mask
www.eeworm.com/read/320641/13420620
qmsg compare_8_bits.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
www.eeworm.com/read/319379/13452849
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity booth is
generic(
WidthMultiplicand: integer := 16;
WidthMultiplier : integer := 16;
WidthCount : integer := 5;
www.eeworm.com/read/319379/13452852
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mul is
generic(
WidthMultiplicand: integer := 16;
WidthMultiplier : integer := 16;
WidthCount : integer := 5
);
www.eeworm.com/read/316087/13530466
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity vstest is
generic(
PERIOD : integer := 40;
DUTY_CYCLE : real := 0.500000;
OFFSET : integer := 0
www.eeworm.com/read/316087/13530473
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity vgatest is
generic(
PERIOD : integer := 40;
DUTY_CYCLE : real := 0.500000;
OFFSET : integer := 0
www.eeworm.com/read/314066/13575704
prj tx2bit.prj
`timescale 1ns/1ns
`include "../6-1/m2_1.v"
`include "../6-1/ddrfd.v"
`include "../6-1/load_gen.v"
`include "../6-1/piso.v"
`include "../6-1/tx2bit.v"
`include "D:/Xilinx/verilog/src/iSE/unisim_