tx2bit.prj

以LVDS设计为例学习ISE中的时序分析以及低层布局器的使用方法 在底层布局器中对LVDS管脚进行约束的方法

`timescale 1ns/1ns
`include "../6-1/m2_1.v"
`include "../6-1/ddrfd.v"
`include "../6-1/load_gen.v"
`include "../6-1/piso.v"
`include "../6-1/tx2bit.v"
`include "D:/Xilinx/verilog/src/iSE/unisim_comp.v"