compare_8_bits.tan.qmsg

用VERILOG语言实现了8BIT编码器.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 08 13:27:34 2006 " "Info: Processing started: Tue Aug 08 13:27:34 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Compare_8_bits -c Compare_8_bits " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Compare_8_bits -c Compare_8_bits" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "A\[0\] LT 13.300 ns Longest " "Info: Longest tpd from source pin \"A\[0\]\" to destination pin \"LT\" is 13.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns A\[0\] 1 PIN PIN_24 6 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 6; PIN Node = 'A\[0\]'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" Compiler "Compare_8_bits" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/" "" "" { A[0] } "NODE_NAME" } "" } } { "Compare_8_bits.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/Compare_8_bits.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.900 ns reduce_nor~47 2 COMB LC3 1 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC3; Fanout = 1; COMB Node = 'reduce_nor~47'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" Compiler "Compare_8_bits" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/" "" "3.700 ns" { A[0] reduce_nor~47 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 4.800 ns reduce_nor~49 3 COMB LC4 1 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC4; Fanout = 1; COMB Node = 'reduce_nor~49'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" Compiler "Compare_8_bits" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/" "" "0.900 ns" { reduce_nor~47 reduce_nor~49 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 5.700 ns reduce_nor~55 4 COMB LC5 1 " "Info: 4: + IC(0.000 ns) + CELL(0.900 ns) = 5.700 ns; Loc. = LC5; Fanout = 1; COMB Node = 'reduce_nor~55'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" Compiler "Compare_8_bits" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/" "" "0.900 ns" { reduce_nor~49 reduce_nor~55 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 7.600 ns reduce_nor~32 5 COMB LC6 9 " "Info: 5: + IC(0.000 ns) + CELL(1.900 ns) = 7.600 ns; Loc. = LC6; Fanout = 9; COMB Node = 'reduce_nor~32'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" Compiler "Compare_8_bits" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/" "" "1.900 ns" { reduce_nor~55 reduce_nor~32 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 11.200 ns LT~17 6 COMB LC9 1 " "Info: 6: + IC(1.000 ns) + CELL(2.600 ns) = 11.200 ns; Loc. = LC9; Fanout = 1; COMB Node = 'LT~17'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" Compiler "Compare_8_bits" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/" "" "3.600 ns" { reduce_nor~32 LT~17 } "NODE_NAME" } "" } } { "Compare_8_bits.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/Compare_8_bits.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 13.100 ns LT~16 7 COMB LC10 1 " "Info: 7: + IC(0.000 ns) + CELL(1.900 ns) = 13.100 ns; Loc. = LC10; Fanout = 1; COMB Node = 'LT~16'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" Compiler "Compare_8_bits" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/" "" "1.900 ns" { LT~17 LT~16 } "NODE_NAME" } "" } } { "Compare_8_bits.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/Compare_8_bits.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 13.300 ns LT 8 PIN PIN_14 0 " "Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 13.300 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'LT'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" Compiler "Compare_8_bits" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/" "" "0.200 ns" { LT~16 LT } "NODE_NAME" } "" } } { "Compare_8_bits.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/Compare_8_bits.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.200 ns 84.21 % " "Info: Total cell delay = 11.200 ns ( 84.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 15.79 % " "Info: Total interconnect delay = 2.100 ns ( 15.79 % )" {  } {  } 0}  } { { "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits_cmp.qrpt" Compiler "Compare_8_bits" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/db/Compare_8_bits.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Compare_8_bits/" "" "13.300 ns" { A[0] reduce_nor~47 reduce_nor~49 reduce_nor~55 reduce_nor~32 LT~17 LT~16 LT } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "13.300 ns" { A[0] A[0]~out reduce_nor~47 reduce_nor~49 reduce_nor~55 reduce_nor~32 LT~17 LT~16 LT } { 0.000ns 0.000ns 1.100ns 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 0.000ns } { 0.000ns 0.200ns 2.600ns 0.900ns 0.900ns 1.900ns 2.600ns 1.900ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 08 13:27:34 2006 " "Info: Processing ended: Tue Aug 08 13:27:34 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}