代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/468753/6987352
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pg6 is
port(
a : in vl_logic_vector(5 downto 0);
b : in vl_logic_vector(5 downto 0);
p
www.eeworm.com/read/468753/6987355
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pg5 is
port(
a : in vl_logic_vector(4 downto 0);
b : in vl_logic_vector(4 downto 0);
p
www.eeworm.com/read/468753/6987365
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pg7 is
port(
a : in vl_logic_vector(6 downto 0);
b : in vl_logic_vector(6 downto 0);
p
www.eeworm.com/read/468753/6987410
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux84 is
port(
i0 : in vl_logic_vector(3 downto 0);
i1 : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/468753/6987418
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux44 is
port(
i0 : in vl_logic_vector(3 downto 0);
i1 : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/468753/6987486
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux16 is
port(
i0 : in vl_logic_vector(31 downto 0);
i1 : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/468753/6987500
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux13_to_1 is
port(
in0 : in vl_logic_vector(31 downto 0);
in1 : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/464849/7061009
cmd_log pwm_sch.cmd_log
sch2verilog -intstyle ise -family xc9500 -w pwm_sch.sch pwm_sch.vf
www.eeworm.com/read/374790/7097662
hif paobiao.hif
Version 7.0 Build 33 02/05/2007 SJ Full Version
39
2288
OFF
OFF
OFF
OFF
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
--
www.eeworm.com/read/374790/7097679
qmsg paobiao.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I