_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 22 行

library verilog;
use verilog.vl_types.all;
entity mux13_to_1 is
    port(
        in0             : in     vl_logic_vector(31 downto 0);
        in1             : in     vl_logic_vector(31 downto 0);
        in2             : in     vl_logic_vector(31 downto 0);
        in3             : in     vl_logic_vector(31 downto 0);
        in4             : in     vl_logic_vector(31 downto 0);
        in5             : in     vl_logic_vector(31 downto 0);
        in6             : in     vl_logic_vector(31 downto 0);
        in7             : in     vl_logic_vector(31 downto 0);
        in8             : in     vl_logic_vector(31 downto 0);
        in9             : in     vl_logic_vector(31 downto 0);
        in10            : in     vl_logic_vector(31 downto 0);
        in11            : in     vl_logic_vector(31 downto 0);
        in12            : in     vl_logic_vector(31 downto 0);
        sel             : in     vl_logic_vector(4 downto 0);
        \out\           : out    vl_logic_vector(31 downto 0)
    );
end mux13_to_1;