_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity pg5 is
    port(
        a               : in     vl_logic_vector(4 downto 0);
        b               : in     vl_logic_vector(4 downto 0);
        p               : out    vl_logic_vector(4 downto 0);
        g               : out    vl_logic_vector(4 downto 0)
    );
end pg5;