代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/168915/9888848
qmsg counttongbu.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Runni
www.eeworm.com/read/364723/9897109
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity chooser is
port(
a : in vl_logic_vector(3 downto 0);
b : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/364280/9914299
qmsg ps2.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/364280/9915550
qmsg vga.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/363301/9961261
rpt display_driver.map.rpt
Analysis & Synthesis report for display_driver
Sun Oct 05 11:51:44 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1
www.eeworm.com/read/361325/10058261
qmsg dispdecoder.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
www.eeworm.com/read/359197/10161688
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ddr_sdram_tb is
port(
);
end ddr_sdram_tb;
www.eeworm.com/read/359174/10162668
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity top is
port(
clk : in vl_logic;
rst : in vl_logic;
adcck : out vl_logic;
www.eeworm.com/read/359174/10162697
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity data is
port(
sclk : in vl_logic;
sdata : out vl_logic
);
end data;
www.eeworm.com/read/359174/10162704
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity vsp2232 is
port(
clk : in vl_logic;
rst : in vl_logic;
clpdm : out vl_logic;