_primary.vhd

来自「chooser the one form two」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity chooser is
    port(
        a               : in     vl_logic_vector(3 downto 0);
        b               : in     vl_logic_vector(3 downto 0);
        c               : in     vl_logic_vector(3 downto 0);
        d               : in     vl_logic_vector(3 downto 0);
        e               : in     vl_logic_vector(3 downto 0);
        f               : in     vl_logic_vector(3 downto 0);
        g               : in     vl_logic_vector(3 downto 0);
        h               : in     vl_logic_vector(3 downto 0);
        choose          : in     vl_logic_vector(2 downto 0);
        \out\           : out    vl_logic_vector(3 downto 0)
    );
end chooser;