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srr hdl_demo.srr

$ Start of Compile #Wed Jun 16 17:36:28 2004 Synplicity Verilog Compiler, version Compilers 2.6.0, Build 102R, built Jan 27 2004 Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved @
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plg hdl_demo.plg

@P: Worst Slack : -16.044 @P: hdl_demo|clk - Estimated Frequency : 44.0 MHz @P: hdl_demo|clk - Requested Frequency : 150.0 MHz @P: hdl_demo|clk - Estimated Period : 22.711 @P: hdl_demo|clk -
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edn hdl_demo.edn

(edif hdl_demo (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2004 6 16 17 36 31) (author "Synplicity, Inc.") (progra
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tlg hdl_demo.tlg

Selecting top level module hdl_demo Synthesizing module alu Synthesizing module hdl_demo @N: CL201 :"D:\CD\Example-4-1\Synplify_Pro\verilog\HDL_DEMO.V":38:0:38:5|Trying to extract state machine for
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prf hdl_demo.prf

# # Logical Preferences generated for Lucent by Synplify 7.3.5, Build 222R. # # Period Constraints FREQUENCY PORT "clk" 150.0 MHz; # Output Constraints CLOCK_TO_OUT "result_0" 6.6667 NS CLKPOR
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srs hdl_demo.srs

# # # # Created by Synplify Verilog HDL Compiler version Compilers 2.6.0, Build 102R from Synplicity, Inc. # Copyright 1994-1999 Synplicity, Inc. , All rights reserved. # Synthesis Netlist writte
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srd hdl_demo.srd

f "noname"; #file 0 f "d:\cd\example-4-1\synplify_pro\verilog\alu.v"; #file 1 f "d:\cd\example-4-1\synplify_pro\verilog\hdl_demo.v"; #file 2 VNAME 'work.alu.verilog'; # view id 0 VNAME 'work.hdl_d
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srm hdl_demo.srm

f "noname"; #file 0 f "d:\cd\example-4-1\synplify_pro\verilog\alu.v"; #file 1 f "d:\cd\example-4-1\synplify_pro\verilog\hdl_demo.v"; #file 2 VNAME 'LUCENT.VHI.PRIM'; # view id 0 VNAME 'LUCENT.VLO.
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ncf hdl_demo.ncf

# # Constraints generated by Synplify Pro 7.3.5, Build 256R # # Period Constraints #Begin clock constraints NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 6.667 ns HIGH 50.00%;
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fse hdl_demo.fse

fsm_encoding {1380381} onehot fsm_state_encoding {1380381} 0000 {0000000001} fsm_state_encoding {1380381} 0001 {0000000010} fsm_state_encoding {1380381} 0010 {0000000100} fsm_state_encod
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