hdl_demo.srr

Xilinx Ise 官方源代码盘 第四章

$ Start of Compile
#Wed Jun 16 17:36:28 2004

Synplicity Verilog Compiler, version Compilers 2.6.0, Build 102R, built Jan 27 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved

@I::"D:\CD\Example-4-1\Synplify_Pro\verilog\ALU.V"
@I::"D:\CD\Example-4-1\Synplify_Pro\verilog\HDL_DEMO.V"
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module hdl_demo
Synthesizing module alu
Synthesizing module hdl_demo
@N: CL201 :"D:\CD\Example-4-1\Synplify_Pro\verilog\HDL_DEMO.V":38:0:38:5|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 10 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   1000
   1001
   1010
   1011
   1100
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################[
Synplicity Lattice ORCA FPGA Technology Mapper, version 7.3.5, Build 222R, built Feb  5 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved
Setting fanout limit to 100
Encoding state machine work.hdl_demo(verilog)-state_h.state[9:0]
original code -> new code
   0000 -> 0000000001
   0001 -> 0000000010
   0010 -> 0000000100
   0011 -> 0000001000
   0100 -> 0000010000
   1000 -> 0000100000
   1001 -> 0001000000
   1010 -> 0010000000
   1011 -> 0100000000
   1100 -> 1000000000

Warning: Forcing use of GSR for flip-flops and
latches that do not specify sets or resets
   work.alu(verilog)-outp[7]
   work.alu(verilog)-outp[6]
   work.alu(verilog)-outp[5]
   work.alu(verilog)-outp[4]
   work.alu(verilog)-outp[3]
   work.alu(verilog)-outp[2]
   work.alu(verilog)-outp[1]
   work.alu(verilog)-outp[0]

Automatic dissolve during optimization of view:work.alu(verilog) of un4_outp_1(ADDMAC8)
Automatic dissolve during optimization of view:work.alu(verilog) of outp_1_1(ADDMAC8)
---------------------------------------
Resource Usage Report
Part: 3txx2-7

Register bits: 24 of 2636 (1%)
I/O cells:       61

Details:
FADD4:          2
FD1P3AX:        14
FD1P3AY:        1
FD1S3AX:        1
FSUB4:          2
GSR:            1
IBM:            53
INV:            1
OB6:            8
OFS1P3DX:       8
ORCALUT4:       62
VHI:            1
VLO:            1
Found clock hdl_demo|clk with period 6.67ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Jun 16 17:36:31 2004
#


Top view:               hdl_demo
Requested Frequency:    150.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT196 |Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock..



Performance Summary 
*******************


Worst slack in design: -16.044

                   Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type         Group              
-----------------------------------------------------------------------------------------------------------------------
hdl_demo|clk       150.0 MHz     44.0 MHz      6.667         22.711        -16.044     inferred     Inferred_clkgroup_0
System             150.0 MHz     60.4 MHz      6.667         16.564        -9.898      system       default_clkgroup   
=======================================================================================================================





Clock Relationships
*******************

Clocks                      |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------
Starting      Ending        |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------
hdl_demo|clk  hdl_demo|clk  |  6.667       -16.044  |  No paths    -      |  No paths    -      |  No paths    -    
====================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port                Starting                  User           Arrival     Required            
Name                Reference                 Constraint     Time        Time         Slack  
                    Clock                                                                    
---------------------------------------------------------------------------------------------
accum_a[0]          hdl_demo|clk (rising)     0.000          0.000       -16.044      -16.044
accum_a[1]          hdl_demo|clk (rising)     0.000          0.000       -16.044      -16.044
accum_a[2]          hdl_demo|clk (rising)     0.000          0.000       -16.044      -16.044
accum_a[3]          hdl_demo|clk (rising)     0.000          0.000       -16.044      -16.044
accum_a[4]          hdl_demo|clk (rising)     0.000          0.000       -11.162      -11.162
accum_a[5]          hdl_demo|clk (rising)     0.000          0.000       -11.162      -11.162
accum_a[6]          hdl_demo|clk (rising)     0.000          0.000       -11.162      -11.162
accum_a[7]          hdl_demo|clk (rising)     0.000          0.000       -11.162      -11.162
accum_b[0]          hdl_demo|clk (rising)     0.000          0.000       -16.044      -16.044
accum_b[1]          hdl_demo|clk (rising)     0.000          0.000       -16.044      -16.044
accum_b[2]          hdl_demo|clk (rising)     0.000          0.000       -16.044      -16.044
accum_b[3]          hdl_demo|clk (rising)     0.000          0.000       -16.044      -16.044
accum_b[4]          hdl_demo|clk (rising)     0.000          0.000       -11.162      -11.162
accum_b[5]          hdl_demo|clk (rising)     0.000          0.000       -11.162      -11.162
accum_b[6]          hdl_demo|clk (rising)     0.000          0.000       -11.162      -11.162
accum_b[7]          hdl_demo|clk (rising)     0.000          0.000       -11.162      -11.162
clk                 NA                        NA             NA          NA           NA     
in_a                hdl_demo|clk (rising)     0.000          0.000       -6.924       -6.924 
in_b                hdl_demo|clk (rising)     0.000          0.000       -6.280       -6.280 
in_c                hdl_demo|clk (rising)     0.000          0.000       -6.280       -6.280 
rst                 System (rising)           NA             0.000       -9.898       -9.898 
start_value[0]      hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[1]      hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[2]      hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[3]      hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[4]      hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[5]      hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[6]      hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[7]      hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[8]      hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[9]      hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[10]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[11]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[12]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[13]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[14]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434