hdl_demo.prf

Xilinx Ise 官方源代码盘 第四章

#
# Logical Preferences generated for Lucent by Synplify 7.3.5, Build 222R.
#

# Period Constraints
FREQUENCY PORT "clk" 150.0 MHz;
# Output Constraints
CLOCK_TO_OUT "result_0" 6.6667 NS CLKPORT = "clk";
CLOCK_TO_OUT "result_1" 6.6667 NS CLKPORT = "clk";
CLOCK_TO_OUT "result_2" 6.6667 NS CLKPORT = "clk";
CLOCK_TO_OUT "result_3" 6.6667 NS CLKPORT = "clk";
CLOCK_TO_OUT "result_4" 6.6667 NS CLKPORT = "clk";
CLOCK_TO_OUT "result_5" 6.6667 NS CLKPORT = "clk";
CLOCK_TO_OUT "result_6" 6.6667 NS CLKPORT = "clk";
CLOCK_TO_OUT "result_7" 6.6667 NS CLKPORT = "clk";
# Input Constraints
INPUT_SETUP "start_value_0" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_1" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_2" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_3" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_4" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_5" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_6" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_7" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_8" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_9" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_10" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_11" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_12" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_13" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_14" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_15" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_16" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_17" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_18" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_19" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_20" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_21" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_22" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_23" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_24" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_25" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_26" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_27" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_28" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_29" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_30" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "start_value_31" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "in_a" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "in_b" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "in_c" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_a_0" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_a_1" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_a_2" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_a_3" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_a_4" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_a_5" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_a_6" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_a_7" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_b_0" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_b_1" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_b_2" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_b_3" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_b_4" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_b_5" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_b_6" 6.6667 NS CLKPORT = "clk";
INPUT_SETUP "accum_b_7" 6.6667 NS CLKPORT = "clk";

BLOCK ASYNCPATHS;

# End of generated Logical Preferences.