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xrf hdl_demo.xrf

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, d:\prj_d\synplify_pro\source\verilog\alu.v, synplify source_file = 2, d:\prj_d\synplify_pro\source\verilog\hdl_demo.v, sy
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srr hdl_demo.srr

$ Start of Compile #Wed Mar 23 02:14:11 2005 Synplicity Verilog Compiler, version Compilers 2.6.0, Build 102R, built Jan 27 2004 Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved @
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plg hdl_demo.plg

@P: Part : EP1S10FC780-5 @P: Worst Slack : -5.041 @P: clk - Estimated Frequency : NA @P: clk - Requested Frequency : 150.0 MHz @P: clk - Estimated Period : NA @P: clk - Requested Period : 6
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vqm hdl_demo.vqm

// // Written by Synplify // Synplify 7.3.5, Build 250R. // Wed Mar 23 02:14:13 2005 // // Source file index table: // Object locations will have the form : // file 0 "noname" // f
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tlg hdl_demo.tlg

Selecting top level module hdl_demo Synthesizing module alu Synthesizing module hdl_demo @N: CL201 :"D:\prj_D\Synplify_Pro\source\verilog\HDL_DEMO.V":38:0:38:5|Trying to extract state machine for r
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tcl hdl_demo.tcl

cmp start_batch project start_batch project start_batch hdl_demo cmp add_assignment "" "" "" ROOT "|hdl_demo" cmp add_assignment "" "" "" FAMILY "STRATIX" cmp add_assignment "hdl_demo" "" "
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ta hdl_demo.ta

###########################################################[ Synplicity Altera Technology Mapper, version 7.3.5, Build 250R, built Mar 18 2004 Copyright (C) 1994-2004, Synplicity Inc. All Rights Re
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sxr hdl_demo.sxr

BeginView hdl_demo NoName Inst: state[9] state_9_ stratix_lcell_ff Inst: state[8] state_8_ stratix_lcell_ff Inst: state[7] state_7_ stratix_lcell_ff Inst: state[6] state_6_ stratix_lc
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srs hdl_demo.srs

# # # # Created by Synplify Verilog HDL Compiler version Compilers 2.6.0, Build 102R from Synplicity, Inc. # Copyright 1994-1999 Synplicity, Inc. , All rights reserved. # Synthesis Netlist writte
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srd hdl_demo.srd

f "noname"; #file 0 f "d:\prj_d\synplify_pro\source\verilog\alu.v"; #file 1 f "d:\prj_d\synplify_pro\source\verilog\hdl_demo.v"; #file 2 VNAME 'work.alu.verilog'; # view id 0 VNAME 'work.hdl_demo.
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