hdl_demo.xrf

一本老师推荐的经典的VHDL覆盖基础的入门书籍

vendor_name = Synplicity
source_file = 0, noname, synplify
source_file = 1, d:\prj_d\synplify_pro\source\verilog\alu.v, synplify
source_file = 2, d:\prj_d\synplify_pro\source\verilog\hdl_demo.v, synplify
design_name=hdl_demo
instance = port, rst, , hdl_demo, 2, 3:6:3:8
instance = port, clk, , hdl_demo, 2, 3:11:3:13
instance = port, start_value[31:0], , hdl_demo, 2, 5:13:5:23
instance = port, in_a, , hdl_demo, 2, 3:16:3:19
instance = port, in_b, , hdl_demo, 2, 3:22:3:25
instance = port, in_c, , hdl_demo, 2, 3:28:3:31
instance = port, accum_a[7:0], , hdl_demo, 2, 4:12:4:18
instance = port, accum_b[7:0], , hdl_demo, 2, 4:21:4:27
instance = port, result[7:0], , hdl_demo, 2, 6:13:6:18
instance = comp, state_9_, , hdl_demo, 2, 86:6:86:5
instance = comp, state_8_, , hdl_demo, 2, 77:6:77:5
instance = comp, state_7_, , hdl_demo, 2, 68:6:68:5
instance = comp, state_6_, , hdl_demo, 2, 59:8:59:7
instance = comp, state_5_, , hdl_demo, 2, 50:8:50:7
instance = comp, state_4_, , hdl_demo, 2, 83:5:83:4
instance = comp, state_3_, , hdl_demo, 2, 74:5:74:4
instance = comp, state_2_, , hdl_demo, 2, 65:5:65:4
instance = comp, state_1_, , hdl_demo, 2, 56:7:56:6
instance = comp, state_i_0_, , hdl_demo, 2, 47:7:47:6
instance = comp, op_code_2_, , hdl_demo, 2, 38:0:38:5
instance = comp, op_code_1_, , hdl_demo, 2, 38:0:38:5
instance = comp, op_code_0_, , hdl_demo, 2, 38:0:38:5
instance = comp, start_Z, , hdl_demo, 2, 33:0:33:5
instance = comp, start9_Z, , hdl_demo, 2, 36:10:36:35
instance = comp, start9_29_Z, , hdl_demo, 2, 36:10:36:35
instance = comp, start9_26_Z, , hdl_demo, 2, 36:10:36:35
instance = comp, start9_26_a_Z, , hdl_demo, 2, 36:10:36:35
instance = comp, state_ns_i_0_a_3_, , hdl_demo, 2, 38:0:38:5
instance = comp, state_ns_0_0_a_4_, , hdl_demo, 2, 38:0:38:5
instance = comp, state_ns_0_0_a_2_, , hdl_demo, 2, 38:0:38:5
instance = comp, start9_23_Z, , hdl_demo, 2, 36:10:36:35
instance = comp, start9_22_Z, , hdl_demo, 2, 36:10:36:35
instance = comp, start9_21_Z, , hdl_demo, 2, 36:10:36:35
instance = comp, start9_20_Z, , hdl_demo, 2, 36:10:36:35
instance = comp, start9_18_Z, , hdl_demo, 2, 36:10:36:35
instance = comp, start9_17_Z, , hdl_demo, 2, 36:10:36:35
instance = comp, start9_16_Z, , hdl_demo, 2, 36:10:36:35
instance = comp, accum_b_in_7_, , hdl_demo, 2, 4:21:4:27
instance = comp, accum_b_in_6_, , hdl_demo, 2, 4:21:4:27
instance = comp, accum_b_in_5_, , hdl_demo, 2, 4:21:4:27
instance = comp, accum_b_in_4_, , hdl_demo, 2, 4:21:4:27
instance = comp, accum_b_in_3_, , hdl_demo, 2, 4:21:4:27
instance = comp, accum_b_in_2_, , hdl_demo, 2, 4:21:4:27
instance = comp, accum_b_in_1_, , hdl_demo, 2, 4:21:4:27
instance = comp, accum_b_in_0_, , hdl_demo, 2, 4:21:4:27
instance = comp, accum_a_in_7_, , hdl_demo, 2, 4:12:4:18
instance = comp, accum_a_in_6_, , hdl_demo, 2, 4:12:4:18
instance = comp, accum_a_in_5_, , hdl_demo, 2, 4:12:4:18
instance = comp, accum_a_in_4_, , hdl_demo, 2, 4:12:4:18
instance = comp, accum_a_in_3_, , hdl_demo, 2, 4:12:4:18
instance = comp, accum_a_in_2_, , hdl_demo, 2, 4:12:4:18
instance = comp, accum_a_in_1_, , hdl_demo, 2, 4:12:4:18
instance = comp, accum_a_in_0_, , hdl_demo, 2, 4:12:4:18
instance = comp, in_c_in, , hdl_demo, 2, 3:28:3:31
instance = comp, in_b_in, , hdl_demo, 2, 3:22:3:25
instance = comp, in_a_in, , hdl_demo, 2, 3:16:3:19
instance = comp, start_value_in_31_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_30_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_29_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_28_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_27_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_26_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_25_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_24_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_23_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_22_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_21_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_20_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_19_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_18_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_17_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_16_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_15_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_14_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_13_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_12_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_11_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_10_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_9_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_8_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_7_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_6_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_5_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_4_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_3_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_2_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_1_, , hdl_demo, 2, 5:13:5:23
instance = comp, start_value_in_0_, , hdl_demo, 2, 5:13:5:23
instance = comp, clk_in, , hdl_demo, 2, 3:11:3:13
instance = comp, rst_in, , hdl_demo, 2, 3:6:3:8
instance = comp, result_out_7_, , hdl_demo, 2, 6:13:6:18
instance = comp, result_out_6_, , hdl_demo, 2, 6:13:6:18
instance = comp, result_out_5_, , hdl_demo, 2, 6:13:6:18
instance = comp, result_out_4_, , hdl_demo, 2, 6:13:6:18
instance = comp, result_out_3_, , hdl_demo, 2, 6:13:6:18
instance = comp, result_out_2_, , hdl_demo, 2, 6:13:6:18
instance = comp, result_out_1_, , hdl_demo, 2, 6:13:6:18
instance = comp, result_out_0_, , hdl_demo, 2, 6:13:6:18
instance = comp, alu1, , hdl_demo, 2, 31:4:31:7
design_name=alu
instance = comp, outp_7_, , alu, 1, 9:0:9:5
instance = comp, outp_6_, , alu, 1, 9:0:9:5
instance = comp, outp_5_, , alu, 1, 9:0:9:5
instance = comp, outp_4_, , alu, 1, 9:0:9:5
instance = comp, outp_3_, , alu, 1, 9:0:9:5
instance = comp, outp_2_, , alu, 1, 9:0:9:5
instance = comp, outp_1_, , alu, 1, 9:0:9:5
instance = comp, outp_0_, , alu, 1, 9:0:9:5
instance = comp, outp_8_3_7_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_a_7_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_6_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_a_6_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_5_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_a_5_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_4_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_a_4_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_3_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_a_3_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_2_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_a_2_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_1_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_a_1_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_0_, , alu, 1, 11:4:11:7
instance = comp, outp_8_3_a_0_, , alu, 1, 11:4:11:7
instance = comp, un4_outp_add7_Z, , alu, 1, 13:18:13:22
instance = comp, un4_outp_add6_Z, , alu, 1, 13:18:13:22
instance = comp, un4_outp_add5_Z, , alu, 1, 13:18:13:22
instance = comp, un4_outp_add4_Z, , alu, 1, 13:18:13:22
instance = comp, un4_outp_add3_Z, , alu, 1, 13:18:13:22
instance = comp, un4_outp_add2_Z, , alu, 1, 13:18:13:22
instance = comp, un4_outp_add1_Z, , alu, 1, 13:18:13:22
instance = comp, un4_outp_add0_Z, , alu, 1, 13:18:13:22
instance = comp, outp_1_add7_Z, , alu, 1, 12:18:12:22
instance = comp, outp_1_add6_Z, , alu, 1, 12:18:12:22
instance = comp, outp_1_add5_Z, , alu, 1, 12:18:12:22
instance = comp, outp_1_add4_Z, , alu, 1, 12:18:12:22
instance = comp, outp_1_add3_Z, , alu, 1, 12:18:12:22
instance = comp, outp_1_add2_Z, , alu, 1, 12:18:12:22
instance = comp, outp_1_add1_Z, , alu, 1, 12:18:12:22
instance = comp, outp_1_add0_Z, , alu, 1, 12:18:12:22