hdl_demo.vqm

一本老师推荐的经典的VHDL覆盖基础的入门书籍

//
// Written by Synplify
// Synplify 7.3.5, Build 250R.
// Wed Mar 23 02:14:13 2005
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\prj_d\synplify_pro\source\verilog\alu.v "
// file 2 "\d:\prj_d\synplify_pro\source\verilog\hdl_demo.v "

module alu (
  accum_b_c_0,
  accum_b_c_1,
  accum_b_c_2,
  accum_b_c_3,
  accum_b_c_4,
  accum_b_c_5,
  accum_b_c_6,
  accum_b_c_7,
  accum_a_c_0,
  accum_a_c_1,
  accum_a_c_2,
  accum_a_c_3,
  accum_a_c_4,
  accum_a_c_5,
  accum_a_c_6,
  accum_a_c_7,
  op_code_0,
  op_code_1,
  op_code_2,
  outp_0,
  outp_1,
  outp_2,
  outp_3,
  outp_4,
  outp_5,
  outp_6,
  outp_7,
  clk_c
);
input accum_b_c_0 ;
input accum_b_c_1 ;
input accum_b_c_2 ;
input accum_b_c_3 ;
input accum_b_c_4 ;
input accum_b_c_5 ;
input accum_b_c_6 ;
input accum_b_c_7 ;
input accum_a_c_0 ;
input accum_a_c_1 ;
input accum_a_c_2 ;
input accum_a_c_3 ;
input accum_a_c_4 ;
input accum_a_c_5 ;
input accum_a_c_6 ;
input accum_a_c_7 ;
input op_code_0 ;
input op_code_1 ;
input op_code_2 ;
output outp_0 ;
output outp_1 ;
output outp_2 ;
output outp_3 ;
output outp_4 ;
output outp_5 ;
output outp_6 ;
output outp_7 ;
input clk_c ;
wire accum_b_c_0 ;
wire accum_b_c_1 ;
wire accum_b_c_2 ;
wire accum_b_c_3 ;
wire accum_b_c_4 ;
wire accum_b_c_5 ;
wire accum_b_c_6 ;
wire accum_b_c_7 ;
wire accum_a_c_0 ;
wire accum_a_c_1 ;
wire accum_a_c_2 ;
wire accum_a_c_3 ;
wire accum_a_c_4 ;
wire accum_a_c_5 ;
wire accum_a_c_6 ;
wire accum_a_c_7 ;
wire op_code_0 ;
wire op_code_1 ;
wire op_code_2 ;
wire outp_0 ;
wire outp_1 ;
wire outp_2 ;
wire outp_3 ;
wire outp_4 ;
wire outp_5 ;
wire outp_6 ;
wire outp_7 ;
wire clk_c ;
wire [7:0] outp_8_3;
wire [7:0] outp_8_3_a;
wire outp_1_add7 ;
wire un4_outp_add7 ;
wire outp_1_add6 ;
wire un4_outp_add6 ;
wire outp_1_add5 ;
wire un4_outp_add5 ;
wire outp_1_add4 ;
wire un4_outp_add4 ;
wire un4_outp_add3 ;
wire outp_1_add3 ;
wire un4_outp_add2 ;
wire outp_1_add2 ;
wire un4_outp_add1 ;
wire outp_1_add1 ;
wire un4_outp_add0 ;
wire outp_1_add0 ;
wire un4_outp_carry_6 ;
wire un4_outp_carry_5 ;
wire un4_outp_carry_4 ;
wire un4_outp_carry_3 ;
wire un4_outp_carry_2 ;
wire un4_outp_carry_1 ;
wire un4_outp_carry_0 ;
wire outp_1_carry_6 ;
wire outp_1_carry_5 ;
wire outp_1_carry_4 ;
wire outp_1_carry_3 ;
wire outp_1_carry_2 ;
wire outp_1_carry_1 ;
wire outp_1_carry_0 ;
wire GND ;
wire VCC ;
// @1:9
  stratix_lcell outp_7_ (
	.regout(outp_7),
	.clk(clk_c),
	.datab(op_code_2),
	.datac(accum_a_c_7),
	.datad(outp_8_3[7])
);
defparam outp_7_.operation_mode="normal";
defparam outp_7_.output_mode="reg_only";
defparam outp_7_.lut_mask="3f0c";
defparam outp_7_.synch_mode="off";
defparam outp_7_.sum_lutc_input="datac";
// @1:9
  stratix_lcell outp_6_ (
	.regout(outp_6),
	.clk(clk_c),
	.datab(op_code_2),
	.datac(accum_a_c_6),
	.datad(outp_8_3[6])
);
defparam outp_6_.operation_mode="normal";
defparam outp_6_.output_mode="reg_only";
defparam outp_6_.lut_mask="3f0c";
defparam outp_6_.synch_mode="off";
defparam outp_6_.sum_lutc_input="datac";
// @1:9
  stratix_lcell outp_5_ (
	.regout(outp_5),
	.clk(clk_c),
	.datab(op_code_2),
	.datac(accum_a_c_5),
	.datad(outp_8_3[5])
);
defparam outp_5_.operation_mode="normal";
defparam outp_5_.output_mode="reg_only";
defparam outp_5_.lut_mask="3f0c";
defparam outp_5_.synch_mode="off";
defparam outp_5_.sum_lutc_input="datac";
// @1:9
  stratix_lcell outp_4_ (
	.regout(outp_4),
	.clk(clk_c),
	.datab(op_code_2),
	.datac(accum_a_c_4),
	.datad(outp_8_3[4])
);
defparam outp_4_.operation_mode="normal";
defparam outp_4_.output_mode="reg_only";
defparam outp_4_.lut_mask="3f0c";
defparam outp_4_.synch_mode="off";
defparam outp_4_.sum_lutc_input="datac";
// @1:9
  stratix_lcell outp_3_ (
	.regout(outp_3),
	.clk(clk_c),
	.datab(op_code_2),
	.datac(accum_a_c_3),
	.datad(outp_8_3[3])
);
defparam outp_3_.operation_mode="normal";
defparam outp_3_.output_mode="reg_only";
defparam outp_3_.lut_mask="3f0c";
defparam outp_3_.synch_mode="off";
defparam outp_3_.sum_lutc_input="datac";
// @1:9
  stratix_lcell outp_2_ (
	.regout(outp_2),
	.clk(clk_c),
	.datab(op_code_2),
	.datac(accum_a_c_2),
	.datad(outp_8_3[2])
);
defparam outp_2_.operation_mode="normal";
defparam outp_2_.output_mode="reg_only";
defparam outp_2_.lut_mask="3f0c";
defparam outp_2_.synch_mode="off";
defparam outp_2_.sum_lutc_input="datac";
// @1:9
  stratix_lcell outp_1_ (
	.regout(outp_1),
	.clk(clk_c),
	.datab(op_code_2),
	.datac(accum_a_c_1),
	.datad(outp_8_3[1])
);
defparam outp_1_.operation_mode="normal";
defparam outp_1_.output_mode="reg_only";
defparam outp_1_.lut_mask="3f0c";
defparam outp_1_.synch_mode="off";
defparam outp_1_.sum_lutc_input="datac";
// @1:9
  stratix_lcell outp_0_ (
	.regout(outp_0),
	.clk(clk_c),
	.datab(op_code_2),
	.datac(accum_a_c_0),
	.datad(outp_8_3[0])
);
defparam outp_0_.operation_mode="normal";
defparam outp_0_.output_mode="reg_only";
defparam outp_0_.lut_mask="3f0c";
defparam outp_0_.synch_mode="off";
defparam outp_0_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_7_ (
	.combout(outp_8_3[7]),
	.dataa(op_code_1),
	.datab(outp_8_3_a[7]),
	.datac(outp_1_add7),
	.datad(un4_outp_add7)
);
defparam outp_8_3_7_.operation_mode="normal";
defparam outp_8_3_7_.output_mode="comb_only";
defparam outp_8_3_7_.lut_mask="7362";
defparam outp_8_3_7_.synch_mode="off";
defparam outp_8_3_7_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_a_7_ (
	.combout(outp_8_3_a[7]),
	.dataa(op_code_0),
	.datab(op_code_1),
	.datac(accum_b_c_7),
	.datad(accum_a_c_7)
);
defparam outp_8_3_a_7_.operation_mode="normal";
defparam outp_8_3_a_7_.output_mode="comb_only";
defparam outp_8_3_a_7_.lut_mask="155d";
defparam outp_8_3_a_7_.synch_mode="off";
defparam outp_8_3_a_7_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_6_ (
	.combout(outp_8_3[6]),
	.dataa(op_code_1),
	.datab(outp_8_3_a[6]),
	.datac(outp_1_add6),
	.datad(un4_outp_add6)
);
defparam outp_8_3_6_.operation_mode="normal";
defparam outp_8_3_6_.output_mode="comb_only";
defparam outp_8_3_6_.lut_mask="7362";
defparam outp_8_3_6_.synch_mode="off";
defparam outp_8_3_6_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_a_6_ (
	.combout(outp_8_3_a[6]),
	.dataa(op_code_0),
	.datab(op_code_1),
	.datac(accum_b_c_6),
	.datad(accum_a_c_6)
);
defparam outp_8_3_a_6_.operation_mode="normal";
defparam outp_8_3_a_6_.output_mode="comb_only";
defparam outp_8_3_a_6_.lut_mask="155d";
defparam outp_8_3_a_6_.synch_mode="off";
defparam outp_8_3_a_6_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_5_ (
	.combout(outp_8_3[5]),
	.dataa(op_code_1),
	.datab(outp_8_3_a[5]),
	.datac(outp_1_add5),
	.datad(un4_outp_add5)
);
defparam outp_8_3_5_.operation_mode="normal";
defparam outp_8_3_5_.output_mode="comb_only";
defparam outp_8_3_5_.lut_mask="7362";
defparam outp_8_3_5_.synch_mode="off";
defparam outp_8_3_5_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_a_5_ (
	.combout(outp_8_3_a[5]),
	.dataa(op_code_0),
	.datab(op_code_1),
	.datac(accum_b_c_5),
	.datad(accum_a_c_5)
);
defparam outp_8_3_a_5_.operation_mode="normal";
defparam outp_8_3_a_5_.output_mode="comb_only";
defparam outp_8_3_a_5_.lut_mask="155d";
defparam outp_8_3_a_5_.synch_mode="off";
defparam outp_8_3_a_5_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_4_ (
	.combout(outp_8_3[4]),
	.dataa(op_code_1),
	.datab(outp_8_3_a[4]),
	.datac(outp_1_add4),
	.datad(un4_outp_add4)
);
defparam outp_8_3_4_.operation_mode="normal";
defparam outp_8_3_4_.output_mode="comb_only";
defparam outp_8_3_4_.lut_mask="7362";
defparam outp_8_3_4_.synch_mode="off";
defparam outp_8_3_4_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_a_4_ (
	.combout(outp_8_3_a[4]),
	.dataa(op_code_0),
	.datab(op_code_1),
	.datac(accum_b_c_4),
	.datad(accum_a_c_4)
);
defparam outp_8_3_a_4_.operation_mode="normal";
defparam outp_8_3_a_4_.output_mode="comb_only";
defparam outp_8_3_a_4_.lut_mask="155d";
defparam outp_8_3_a_4_.synch_mode="off";
defparam outp_8_3_a_4_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_3_ (
	.combout(outp_8_3[3]),
	.dataa(op_code_1),
	.datab(outp_8_3_a[3]),
	.datac(un4_outp_add3),
	.datad(outp_1_add3)
);
defparam outp_8_3_3_.operation_mode="normal";
defparam outp_8_3_3_.output_mode="comb_only";
defparam outp_8_3_3_.lut_mask="7632";
defparam outp_8_3_3_.synch_mode="off";
defparam outp_8_3_3_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_a_3_ (
	.combout(outp_8_3_a[3]),
	.dataa(op_code_0),
	.datab(op_code_1),
	.datac(accum_b_c_3),
	.datad(accum_a_c_3)
);
defparam outp_8_3_a_3_.operation_mode="normal";
defparam outp_8_3_a_3_.output_mode="comb_only";
defparam outp_8_3_a_3_.lut_mask="155d";
defparam outp_8_3_a_3_.synch_mode="off";
defparam outp_8_3_a_3_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_2_ (
	.combout(outp_8_3[2]),
	.dataa(op_code_1),
	.datab(outp_8_3_a[2]),
	.datac(un4_outp_add2),
	.datad(outp_1_add2)
);
defparam outp_8_3_2_.operation_mode="normal";
defparam outp_8_3_2_.output_mode="comb_only";
defparam outp_8_3_2_.lut_mask="7632";
defparam outp_8_3_2_.synch_mode="off";
defparam outp_8_3_2_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_a_2_ (
	.combout(outp_8_3_a[2]),
	.dataa(op_code_0),
	.datab(op_code_1),
	.datac(accum_b_c_2),
	.datad(accum_a_c_2)
);
defparam outp_8_3_a_2_.operation_mode="normal";
defparam outp_8_3_a_2_.output_mode="comb_only";
defparam outp_8_3_a_2_.lut_mask="155d";
defparam outp_8_3_a_2_.synch_mode="off";
defparam outp_8_3_a_2_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_1_ (
	.combout(outp_8_3[1]),
	.dataa(op_code_1),
	.datab(outp_8_3_a[1]),
	.datac(un4_outp_add1),
	.datad(outp_1_add1)
);
defparam outp_8_3_1_.operation_mode="normal";
defparam outp_8_3_1_.output_mode="comb_only";
defparam outp_8_3_1_.lut_mask="7632";
defparam outp_8_3_1_.synch_mode="off";
defparam outp_8_3_1_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_a_1_ (
	.combout(outp_8_3_a[1]),
	.dataa(op_code_0),
	.datab(op_code_1),
	.datac(accum_b_c_1),
	.datad(accum_a_c_1)
);
defparam outp_8_3_a_1_.operation_mode="normal";
defparam outp_8_3_a_1_.output_mode="comb_only";
defparam outp_8_3_a_1_.lut_mask="155d";
defparam outp_8_3_a_1_.synch_mode="off";
defparam outp_8_3_a_1_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_0_ (
	.combout(outp_8_3[0]),
	.dataa(op_code_1),
	.datab(outp_8_3_a[0]),
	.datac(un4_outp_add0),
	.datad(outp_1_add0)
);
defparam outp_8_3_0_.operation_mode="normal";
defparam outp_8_3_0_.output_mode="comb_only";
defparam outp_8_3_0_.lut_mask="7632";
defparam outp_8_3_0_.synch_mode="off";
defparam outp_8_3_0_.sum_lutc_input="datac";
// @1:11
  stratix_lcell outp_8_3_a_0_ (
	.combout(outp_8_3_a[0]),
	.dataa(op_code_0),
	.datab(op_code_1),
	.datac(accum_b_c_0),
	.datad(accum_a_c_0)
);
defparam outp_8_3_a_0_.operation_mode="normal";
defparam outp_8_3_a_0_.output_mode="comb_only";
defparam outp_8_3_a_0_.lut_mask="155d";
defparam outp_8_3_a_0_.synch_mode="off";
defparam outp_8_3_a_0_.sum_lutc_input="datac";
// @1:13
  stratix_lcell un4_outp_add7_Z (
	.combout(un4_outp_add7),
	.dataa(accum_b_c_7),
	.datab(accum_a_c_7),
	.cin(un4_outp_carry_6)
);
defparam un4_outp_add7_Z.cin_used="true";
defparam un4_outp_add7_Z.operation_mode="normal";
defparam un4_outp_add7_Z.output_mode="comb_only";
defparam un4_outp_add7_Z.lut_mask="6969";
defparam un4_outp_add7_Z.synch_mode="off";
defparam un4_outp_add7_Z.sum_lutc_input="cin";
// @1:13
  stratix_lcell un4_outp_add6_Z (
	.combout(un4_outp_add6),
	.cout(un4_outp_carry_6),
	.dataa(accum_b_c_6),
	.datab(accum_a_c_6),
	.cin(un4_outp_carry_5)
);
defparam un4_outp_add6_Z.cin_used="true";
defparam un4_outp_add6_Z.operation_mode="arithmetic";
defparam un4_outp_add6_Z.output_mode="comb_only";
defparam un4_outp_add6_Z.lut_mask="69d4";
defparam un4_outp_add6_Z.synch_mode="off";
defparam un4_outp_add6_Z.sum_lutc_input="cin";
// @1:13
  stratix_lcell un4_outp_add5_Z (
	.combout(un4_outp_add5),
	.cout(un4_outp_carry_5),
	.dataa(accum_b_c_5),
	.datab(accum_a_c_5),
	.cin(un4_outp_carry_4)
);
defparam un4_outp_add5_Z.cin_used="true";
defparam un4_outp_add5_Z.operation_mode="arithmetic";
defparam un4_outp_add5_Z.output_mode="comb_only";
defparam un4_outp_add5_Z.lut_mask="69d4";
defparam un4_outp_add5_Z.synch_mode="off";
defparam un4_outp_add5_Z.sum_lutc_input="cin";
// @1:13
  stratix_lcell un4_outp_add4_Z (
	.combout(un4_outp_add4),
	.cout(un4_outp_carry_4),
	.dataa(accum_b_c_4),
	.datab(accum_a_c_4),
	.cin(un4_outp_carry_3)
);
defparam un4_outp_add4_Z.cin_used="true";
defparam un4_outp_add4_Z.operation_mode="arithmetic";
defparam un4_outp_add4_Z.output_mode="comb_only";
defparam un4_outp_add4_Z.lut_mask="69d4";
defparam un4_outp_add4_Z.synch_mode="off";
defparam un4_outp_add4_Z.sum_lutc_input="cin";
// @1:13
  stratix_lcell un4_outp_add3_Z (
	.combout(un4_outp_add3),
	.cout(un4_outp_carry_3),
	.dataa(accum_b_c_3),
	.datab(accum_a_c_3),
	.cin(un4_outp_carry_2)
);
defparam un4_outp_add3_Z.cin_used="true";
defparam un4_outp_add3_Z.operation_mode="arithmetic";
defparam un4_outp_add3_Z.output_mode="comb_only";
defparam un4_outp_add3_Z.lut_mask="69d4";
defparam un4_outp_add3_Z.synch_mode="off";
defparam un4_outp_add3_Z.sum_lutc_input="cin";
// @1:13
  stratix_lcell un4_outp_add2_Z (
	.combout(un4_outp_add2),
	.cout(un4_outp_carry_2),
	.dataa(accum_b_c_2),
	.datab(accum_a_c_2),
	.cin(un4_outp_carry_1)
);