代码搜索：verilog hdl 开发教程
找到约 10,000 项符合「verilog hdl 开发教程」的源代码
代码结果 10,000
www.eeworm.com/read/13927/287995
pdf x-hdl.pdf
www.eeworm.com/read/18434/788679
v hdl_demo.v
module hdl_demo(rst, clk, start_value, in_a, in_b, in_c, accum_a, accum_b, result);
input rst, clk, in_a, in_b, in_c;
input [7:0] accum_a, accum_b;
input [31:0] start_value;
output [7:0] result;
www.eeworm.com/read/18434/788681
vhd hdl_demo.vhd
library IEEE;
use IEEE.std_logic_1164.all;
--lab2
--lab2
entity hdl_demo is
port (rst, clk,in_a,in_b,in_c : in std_logic;
accum_a, accum_b : in std_logic_vector(7 downto 0);
www.eeworm.com/read/18434/788739
v hdl_demo.v
module hdl_demo(rst, clk, start_value, in_a, in_b, in_c, accum_a, accum_b, result);
input rst, clk, in_a, in_b, in_c;
input [7:0] accum_a, accum_b;
input [31:0] start_value;
output [7:0] result;
www.eeworm.com/read/18434/788741
vhd hdl_demo.vhd
library IEEE;
use IEEE.std_logic_1164.all;
--lab2
--lab2
entity hdl_demo is
port (rst, clk,in_a,in_b,in_c : in std_logic;
accum_a, accum_b : in std_logic_vector(7 downto 0);
www.eeworm.com/read/18434/788744
xrf hdl_demo.xrf
vendor_name = Synplicity
source_file = 0, noname, synplify
source_file = 1, d:\prj_d\synplify_pro\source\verilog\alu.v, synplify
source_file = 2, d:\prj_d\synplify_pro\source\verilog\hdl_demo.v, sy
www.eeworm.com/read/18434/788745
srr hdl_demo.srr
$ Start of Compile
#Wed Mar 23 02:14:11 2005
Synplicity Verilog Compiler, version Compilers 2.6.0, Build 102R, built Jan 27 2004
Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved
@
www.eeworm.com/read/18434/788747
plg hdl_demo.plg
@P: Part : EP1S10FC780-5
@P: Worst Slack : -5.041
@P: clk - Estimated Frequency : NA
@P: clk - Requested Frequency : 150.0 MHz
@P: clk - Estimated Period : NA
@P: clk - Requested Period : 6
www.eeworm.com/read/18434/788748
vqm hdl_demo.vqm
//
// Written by Synplify
// Synplify 7.3.5, Build 250R.
// Wed Mar 23 02:14:13 2005
//
// Source file index table:
// Object locations will have the form :
// file 0 "noname"
// f
www.eeworm.com/read/18434/788753
tlg hdl_demo.tlg
Selecting top level module hdl_demo
Synthesizing module alu
Synthesizing module hdl_demo
@N: CL201 :"D:\prj_D\Synplify_Pro\source\verilog\HDL_DEMO.V":38:0:38:5|Trying to extract state machine for r