代码搜索：testbench

找到约 2,392 项符合「testbench」的源代码

代码结果 2,392
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/193096/8253783

vhd cordic_tst.vhd

-- VHDL Test Bench Created from source file sc_corproc.vhd -- 12/07/06 11:47:39 -- -- Notes: -- 1) This testbench template has been automatically generated using types -- std_logic and std_logic_vec
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www.eeworm.com/read/412328/11204442

mti xuexi.cr.mti

G:/debug/modelsim/latch_rp.v {1 {vlog -work work -vopt G:/debug/modelsim/latch_rp.v Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006 -- Compiling UDP latch_rp Top level modules
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www.eeworm.com/read/249359/12509117

entries

/readme.txt/1.2/Mon Apr 16 20:00:18 2007// D/c_model//// D/docs//// D/image//// D/src//// D/testbench////
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www.eeworm.com/read/135419/13934180

adf sap1.adf

[Project] Current Flow=Generic VCS=0 version=1 modified=9 Current Config=compile [Configurations] compile=sap1 [Library] sap1=.\sap1.LIB [$LibMap$] sap1=. [Settings] FLOW_TYPE=Schematic
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www.eeworm.com/read/202015/15391164

do comp_gate.do

echo *** Compiling core and testbench for simulation ... vlib work vlog diff_io_top.vo vlog testbench.v
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www.eeworm.com/read/430383/8752303

entries

/image.bmp/1.1/Fri Jan 7 15:26:46 2005/-kb/ /jpeg_src.zip/1.2/Mon Mar 14 10:34:09 2005/-kb/ /readme.txt/1.1/Mon Mar 14 10:34:10 2005// D/cores//// D/docs//// D/images//// D/src//// D/testbench////
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www.eeworm.com/read/430376/8753026

cfv demo_amba_for_tb.cfv

// Simucad Generated Commands Start Here // Simucad define +define+sse // Project Settings +typdelays -"!file .sav=\"demo_amba_for_tb\"" -"!control .sav=3" -"!control .enablecache" -l demo
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www.eeworm.com/read/286093/8788661

vhd test.vhd

-- Vhdl test bench created from schematic top.sch - Wed May 16 12:37:26 2007 -- -- Notes: -- 1) This testbench template has been automatically generated using types -- std_logic and std_logic_vec
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www.eeworm.com/read/286093/8788760

vhd top.vhd

-- Vhdl test bench created from schematic top.sch - Wed May 30 16:35:15 2007 -- -- Notes: -- 1) This testbench template has been automatically generated using types -- std_logic and std_logic_vec
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www.eeworm.com/read/286093/8788784

vhd topaaa.vhd

-- Vhdl test bench created from schematic top.sch - Wed Jun 20 18:34:17 2007 -- -- Notes: -- 1) This testbench template has been automatically generated using types -- std_logic and std_logic_vec
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