test.vhd

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-- Vhdl test bench created from schematic top.sch - Wed May 16 12:37:26 2007
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavioral OF testbench IS 

   COMPONENT top
   PORT( en1	:	IN	STD_LOGIC; 
          clkin	:	IN	STD_LOGIC; 
          qqd	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          out71	:	OUT	STD_LOGIC_VECTOR (6 DOWNTO 0); 
          bout	:	OUT	STD_LOGIC; 
          out72	:	OUT	STD_LOGIC_VECTOR (6 DOWNTO 0); 
          out73	:	OUT	STD_LOGIC_VECTOR (6 DOWNTO 0));
   END COMPONENT;

   SIGNAL en1	:	STD_LOGIC;
   SIGNAL clkin	:	STD_LOGIC;
   SIGNAL qqd	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
   SIGNAL out71	:	STD_LOGIC_VECTOR (6 DOWNTO 0);
   SIGNAL bout	:	STD_LOGIC;
   SIGNAL out72	:	STD_LOGIC_VECTOR (6 DOWNTO 0);
   SIGNAL out73	:	STD_LOGIC_VECTOR (6 DOWNTO 0);

BEGIN

   UUT: top PORT MAP(
		en1 => en1, 
		clkin => clkin, 
		qqd => qqd, 
		out71 => out71, 
		bout => bout, 
		out72 => out72, 
		out73 => out73
   );

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
      BEGIN
       wait for 50 ms;en1<='1';
	  wait for 12000 ms;en1<='0';wait for 1000 ms;
	  en1<='1';wait;													

   END PROCESS;
   ta: process
   begin
      clkin<='0';wait for 15.625 ns;
	 clkin<='1';wait for 15.625 ns;
	 end process;
	  tc:process
	  begin
	    wait for 14000 ms;qqd<="00100000";
	    
	    end process;
-- *** End Test Bench - User Defined Section ***

END;