代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
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vhd testbench.vhd
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- The Free IP Project
-- VHDL DES Core
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v testbench.v
//title Simple testbench for the Code Coverage example
`timescale 1ns / 1ns
`disable_codecoverage
module testbench;
reg[1:0] A, B, C, D;
wire[1:0] Z;
select select_ABCD (A, B, C, D, Z);
i
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vhdtst testbench.vhdtst
-- run to time 90 ns
Library IEEE ;
Use IEEE.std_logic_1164.all ;
Use IEEE.std_logic_textio.all ;
Library work;
Use work.all;
Library STD ;
Use std.textio.all
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v testbench.v
`include "Root.v"
module main;
parameter Toff = 10, Ton = 10, VSoff = 36 * 20 * 30, VSon = 36 * 20 * 2, PCoff = 18, PCon = 18, HRoff = 36 * 20 * 2, HRon = 36 * 20;
reg CLK, PCLK, Href, Vsync,M
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pdf testbench.pdf
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txt testbench.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.my_package.all;
entity test2_trans is
end test2_trans;
architecture bench2
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v testbench.v
module testbench;
reg clk=1'b0;
reg rst;
initial
begin
rst=1; #1 rst=0; #2 rst=1;
end
always #5 clk=~clk;
div_3 md(clk,clkout,rst);
endmodule
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v testbench.v
`include "params.v"
`define D_PER
/************************************************************************************/
module VD();
reg CLOCK;
initial CLOCK = 0;
always #(
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v testbench.v
module testbench();
reg clk, rst;
reg send_r;
wire send;
wire req_out, ack_in, reqout_router, ack_out;
wire [33:0] dout;
assign send = send_r;
always #5 clk = ~clk
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v testbench.v
//title Simple testbench for the Code Coverage example
`timescale 1ns / 1ns
`disable_codecoverage
module testbench;
reg[1:0] A, B, C, D;
wire[1:0] Z;
select select_ABCD (A, B, C, D, Z);
i