testbench.v

占空比50 的三分频Verilog代码

module testbench;
    reg clk=1'b0;
    reg rst;
    initial
    begin
        rst=1; #1 rst=0; #2 rst=1;
    end
    always #5 clk=~clk;
    
    div_3 md(clk,clkout,rst);
endmodule