testbench.v

The objective of this project is to create a driver for a camera module (we used the OV7620). After

`include "Root.v"
module main;

parameter Toff = 10, Ton = 10, VSoff = 36 * 20 * 30, VSon = 36 * 20 * 2, PCoff = 18, PCon = 18, HRoff = 36 * 20 * 2, HRon = 36 * 20;

	reg CLK, PCLK, Href, Vsync,Mode;
	wire TX, OE, WE;
	wire [17:0] Addr;
	wire [7:0]	Data;
	reg  [7:0]	Y;

	Root rmodule(CLK,TX,Data,Addr,PCLK,Y,Href,Vsync,OE,WE);

   initial begin
      #5 CLK = 0;
	Y = 0;
	Vsync = 0;
	PCLK = 0;
	Href = 1;
   end
   
   // The following is correct if clock starts at LOW level at StartTime //
   always begin
      #Toff CLK = ~CLK;
      #Ton CLK = ~CLK;
   end

   /*always
	begin
		if($time == 50000)
			$stop;
	end*/

   always begin
	#VSoff Vsync = ~Vsync;
	#VSon  Vsync = ~Vsync;
   end

   always begin
	#PCoff PCLK = ~PCLK;
	#PCon  PCLK = ~PCLK;
   end

   always begin
	#HRoff Href = ~Href;
	#HRon  Href = ~Href;
   end

   always @ (CLK)
   begin
	$display($time);
	$display("-TestBench------------------------------");
	$display("CLK: %b PCLK: %b HREF: %b VSYNC: %b OE: %b WE: %b", CLK, PCLK, Href, Vsync, OE, WE);
	$display("-Root-----------------------------------");
	$display("Mode: %b SerialDone: %b CamDone: %b EitherDone: %b", rmodule.Mode, rmodule.SerialDone, rmodule.CamDone, rmodule.EitherDone);
	$display("-Cam------------------------------------");
	$display("Ready: %b Addr: %d Enable: %b", rmodule.cam.Ready, rmodule.cam.Addr, rmodule.cam.Enable);
	$display("-RS232----------------------------------");
	$display("Send: %b Addr: %d Busy: %b", rmodule.serial.Send, rmodule.serial.Addr, rmodule.serial.Busy);
	$display("\t-async_trans--------------------------");
	$display("\tstate: %d ready: %b start: %b clk: %b BaudGeneratorAcc: %b", rmodule.serial.AT.state, rmodule.serial.AT.TxD_ready, rmodule.serial.AT.TxD_start, rmodule.serial.AT.clk, rmodule.serial.AT.BaudGeneratorAcc);
   end

endmodule