代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/294990/8191177
pl mk_testbench.pl
#Copyright (C)2001-2004 Altera Corporation
#Any megafunction design, and related net list (encrypted or decrypted),
#support information, device programming or simulation file, and any other
#assoc
www.eeworm.com/read/174424/9587838
vhd testbench_decoder.vhd
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------------------------------------------------------------------
www.eeworm.com/read/368538/9690051
exe usb_testbench.exe
www.eeworm.com/read/172338/9713032
ndo can_testbench.ndo
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model for Module can_top
vcom -87 -explicit can_t
www.eeworm.com/read/172338/9713105
udo can_testbench.udo
## Project Navigator simulation template: can_testbench.udo
## You may edit this file to control your simulation.
www.eeworm.com/read/172338/9713167
v can_testbench.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
`include "can_testbench_defines.v"
module can_testbench();
parameter Tp = 1;
paramet
www.eeworm.com/read/172338/9713204
fdo can_testbench.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jan 11 10:15:14 中国标准时间 2005
##
vlib work
vlog can_register_asyn_syn.v
vlog can_register_asyn.v
vlog can_regi
www.eeworm.com/read/413190/11163688
vhd cpu_testbench.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.controller_const.all;
--use work.alu_const.all;
entity Test_CPU is
end entity Test_CPU;
architecture Test_CPU of Test_C
www.eeworm.com/read/267551/11175040
bak testbench.v.bak
`timescale 1ns/10ps
module testbench;
reg [15:0] a;
reg [15:0] b;
reg cin;
wire [15:0] s;
wire cout;
add16_adv
u0(
.vA(a),
.vB(b),
.vS(s),
.cin(cin),
.cout(cout)
);
initial b
www.eeworm.com/read/412328/11204504
v testbench1.v
module testbench;
reg clock;
reg reset;
reg load;
wire[4:0] shiftreg;
reg [2:0] sel;
reg [4:0] data;
shift_reg dut (.clock(clock),
.reset(reset),
.load(load),