testbench1.v

来自「SOPC Builder创建的CPU」· Verilog 代码 · 共 38 行

module testbench;
	reg clock;
	reg reset;
	reg load;
	wire[4:0] shiftreg;
	reg [2:0] sel;
	reg [4:0] data;
	shift_reg dut (.clock(clock),
	            .reset(reset),
	            .load(load),
	            .data(data),
	            .shiftreg(shiftreg));
   initial begin
       clock=0;
       forever #50 clock=~clock;
   end
   initial begin
       reset=1;
       data=5'b00000;
       load=0;
       sel=2'b00;
    #200
       reset=0;
       load=1;
    #200
       data=5'b00001;
    #100
       sel=2'b01;
       load=0;
    #200
       sel=2'b10;
    #1000 $stop;
   end
   
   endmodule