代码搜索：testbench

找到约 2,392 项符合「testbench」的源代码

代码结果 2,392
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/320300/13428717

_info

m255 13 cModel Technology dC:\Documents and Settings\srikanth\Desktop\SMGPIO\modelsim vnand_flash_testbench IN0`beQfJgE9@nZ?:C=Wh`2 VFFd4BWM1e:Hb^KmF16OL>3 dD:\Altera\MAXIIZ update\Design example\AN50
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www.eeworm.com/read/217283/14970677

ref hdllib.ref

AR clockdiv_tbw testbench_arch D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv_tbw.vhw sub00/vhpl03 1181703562 EN clockdiv NULL D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv.vhd sub00/vhpl00 1181702992 AR clockdiv
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www.eeworm.com/read/10793/190741

txt tcl_stacktrace.txt

Thu May 07 21:04:51 中国标准时间 2009 Trace back: ** Error: (vish-7) Failed to open mpf file "F:/EdaOk/project/PeriphDIY/uart/fpga/V0p00/testbench/uart.mpf" in write mode. Permission denied. (errno = EACC
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www.eeworm.com/read/17491/732631

txt tcl_stacktrace.txt

Thu May 07 21:04:51 中国标准时间 2009 Trace back: ** Error: (vish-7) Failed to open mpf file "F:/EdaOk/project/PeriphDIY/uart/fpga/V0p00/testbench/uart.mpf" in write mode. Permission denied. (errno = EACC
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www.eeworm.com/read/167222/9975054

v test_gr.v

module testbench_GR; wire [7:0] GR_out,GR_in; wire [2:0] GR_address; wire clk,reset,load_enable; GR g (GR_out,GR_in,clk,reset,GR_address,load_enable); test t (GR_out,GR_in,clk,re
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www.eeworm.com/read/298156/7972208

txt 文件说明.txt

sim\testbench.v 顶层模块的测试程序 sim\Tdata.v 测试向量 src\laps_management.v LAPS处理顶层模块 src\data_receive.v 从信源接收数据的模块 src\fifo_trans.v 发送缓存FIFO模块 src\enframe.v
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www.eeworm.com/read/342724/12004655

ref hdllib.ref

AR lcd_controller_tbw testbench_arch D:/Stuffz/VHDL/Test_LCD/LCD_Controller_tbw.ant sub00/vhpl03 1184513155 AR lcd_controller behavioral D:/Stuffz/VHDL/Test_LCD/LCD_Controller.vhd sub00/vhpl01 118451
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www.eeworm.com/read/11637/231942

v tb_gene.v

//testbench for vgasdram `timescale 1ns/1ns module tb_gene; reg clk; //系统时钟，50MHz reg rst_n; //复位信号，低电平有效 wire [7:0] wrf_din; wire wrf_wrreq; wire syswr_done; wire[21:0] sys_wraddr;
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www.eeworm.com/read/397063/2404537

v testkes.v

`timescale 1ns/1ns module testbench_kes; reg active_kes, clock1, clock2, reset; reg [7:0] syndvalue0, syndvalue1, syndvalue2, syndvalue3, syndvalue4, syndvalue5, syndvalue6, syndvalue7,
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www.eeworm.com/read/135419/13934271

dag mega.dag

; SAP_1_tb(!53!41!50_1_tb.dag) ;sources section file 0 ".\src\TestBench\SAP_1_TB.v" ;initial UNIT p ;no. 0 src 0 29 #16 20 0 28 ARGP4 #20 24 0 0 INDIRP4 #24 0 0 0
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