tb_gene.v

来自「sdram读写」· Verilog 代码 · 共 42 行

//testbench for vgasdram

`timescale 1ns/1ns


module tb_gene;

reg clk;		//系统时钟，50MHz
reg rst_n;		//复位信号，低电平有效
wire [7:0] wrf_din;
wire wrf_wrreq;
wire syswr_done;
wire[21:0] sys_wraddr;	
wire[21:0] sys_rdaddr;
wire sdram_busy;
wire sdram_rd_ack;

parameter clockperiod=40;

			
datagene	uut_datagene(
				.clk(clk),
				.rst_n(rst_n),
				.wrf_din(wrf_din),
				.wrf_wrreq(wrf_wrreq),
				.sys_wraddr(sys_wraddr),
				.sys_rdaddr(sys_rdaddr),
				.syswr_done(syswr_done),
				.sdram_busy(sdram_busy),
				.sdram_rd_ack(sdram_rd_ack)
			);

always #(clockperiod/2) clk=~clk;

initial begin
	clk=0;
	rst_n=0;
	#100 rst_n=1;
end


endmodule