代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/314805/13558783
vhw write_back_wave.vhw
-- E:\资料\计算机设计与实践\CPU_16\CPU_16
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sat Nov 10 14:32:17 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
www.eeworm.com/read/314805/13558810
vhw clock_wave.vhw
-- E:\资料\计算机设计与实践\CPU_16\CPU_16
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sat Nov 10 14:17:45 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
www.eeworm.com/read/301795/13848353
m xk_cmpr.m
%function fft_cmpr;
ax_font_size = 22;
ax_lab_size = 24;
fmt = '-tiff -deps';
print_flag=0;
n = 16;
fname_c_model = input('C model input data: ','s');
fname_vhdl = input('testbench output d
www.eeworm.com/read/492005/6429653
tf jc2_test.tf
`timescale 1ns/1ns
// Timing simulation test fixture for jc2_top Verilog design.
module testbench;
reg clk;
reg stop;
reg left;
reg right;
wire [3:0] q;
reg PRLD;
jc2_top UUT (
.left(left),
www.eeworm.com/read/246866/4490580
vhd fifo_2048x8_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fifo_2048x8_tb is
end fifo_2048x8_tb;
architecture testbench of fifo_
www.eeworm.com/read/346982/3179052
h tb.h
//testbench of nand2,By chenxi ,all rights reserved
//tb.h
#ifndef _TB_H
#define _TB_H
SC_MODULE(tb){
sc_out a,b;
sc_in f;
sc_in_clk clk;
void gen_input(){
wait(); a=
www.eeworm.com/read/346982/3179059
h tb.h
//testbench of nand2,By chenxi ,all rights reserved
//tb.h
#ifndef _TB_H
#define _TB_H
SC_MODULE(tb){
sc_out a,b;
sc_in f;
sc_in_clk clk;
void gen_input(){
wait(); a=
www.eeworm.com/read/305151/3779925
tf jc2_test.tf
`timescale 1ns/1ns
// Timing simulation test fixture for jc2_top Verilog design.
module testbench;
reg clk;
reg stop;
reg left;
reg right;
wire [3:0] q;
reg PRLD;
jc2_top UUT (
.left(left),
www.eeworm.com/read/305151/3780111
tf jc2_test.tf
`timescale 1ns/1ns
// Timing simulation test fixture for jc2_top Verilog design.
module testbench;
reg clk;
reg stop;
reg left;
reg right;
wire [3:0] q;
reg PRLD;
jc2_top UUT (
.left(left),
www.eeworm.com/read/293898/3927527
tf jc2_test.tf
`timescale 1ns/1ns
// Timing simulation test fixture for jc2_top Verilog design.
module testbench;
reg clk;
reg stop;
reg left;
reg right;
wire [3:0] q;
reg PRLD;
jc2_top UUT (
.left(left),