fifo_2048x8_tb.vhd

Xilinx高级试验的代码.zip 非常不错

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fifo_2048x8_tb is
    
end fifo_2048x8_tb;

architecture testbench of fifo_2048x8_tb is

    component fifo_2048x8
        port (
            rd_clk, wr_clk : in  std_logic;
            wr             : in  std_logic;
            reset          : in  std_logic;
            rd             : in  std_logic;
            wr_addr        : in  std_logic_vector(10 downto 0);
            rd_addr        : in  std_logic_vector(10 downto 0);
            wr_data        : in  std_logic_vector(7 downto 0);
            rd_data        : out std_logic_vector(7 downto 0));
    end component;

    signal rd_clk, wr_clk, reset, wr, rd : std_logic := '0';
    signal wr_addr, rd_addr : std_logic_vector(10 downto 0) := (others => '0');

    ---------------------------------------------------------------------------
    -- Create data to write to RAM
    ---------------------------------------------------------------------------
    type misc_data_type is array (0 to 15) of std_logic_vector(7 downto 0);
    constant misc_data : misc_data_type := ("00000000", "00000001", "00000010", "00000011",
                                            "00000100", "00000101", "00000110", "00000111",
                                            "00001000", "00001001", "00001010", "00001011",
                                            "00001100", "00001101", "00001110", "00001111");
    signal rd_data, wr_data : std_logic_vector(7 downto 0);
    signal done_writing : std_logic := '0';  -- indicates writing to RAM is complete
    
begin  -- testbench

    fifo_2048x8_inst: fifo_2048x8
        port map (
            rd_clk  => rd_clk,
            wr_clk  => wr_clk,
            wr      => wr,
            rd      => rd,
            reset   => reset,
            wr_addr => wr_addr,
            rd_addr => rd_addr,
            wr_data => wr_data,
            rd_data => rd_data);

    reset <= '1', '0' after 27 ns;

    rd_clk <= not rd_clk after 2.5 ns;
    wr_clk <= not wr_clk after 5 ns;

    generate_wr_data: process 
    begin
        wait until falling_edge(reset);

        -- loop through first 16 addresses
        for i in 0 to 15 loop
            wr_data <= misc_data(i);
            wr_addr <= conv_std_logic_vector(i,11);
            -- wait 8 clock cycles before writing to mimick the functionality
            -- of the actual design
            for j in 0 to 7 loop
                if j = 7 then
                    wr <= '1';
                else
                    wr <= '0';
                end if;
                wait until rising_edge(wr_clk);
            end loop;  -- j
        end loop;  -- i
        done_writing <= '1';            -- flag which indicates writing is completed
        wr <= '0';
        wait;
    end process;

    read_data: process 
    begin
        wait until falling_edge(reset);

        wait until rising_edge(done_writing);  -- wait until writing is completed

        -- loop through first 16 addresses
        for i in 0 to 15 loop
            rd_addr <= conv_std_logic_vector(i,11);
            -- wait 8 clock cycles (mimimum) before writing to mimick the functionality
            -- of the actual design
            for j in 0 to 7 loop
                if j = 7 then
                    rd <= '1';
                else
                    rd <= '0';
                end if;
                wait until rising_edge(rd_clk);
            end loop;  -- j
        end loop;  -- i
        rd <= '0';
        wait until rising_edge(rd_clk);
        wait;
    end process;
    
end testbench;