代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/387833/2556054
do traffic_tb_runtest.do
SetActiveLib -work
#Compiling UUT module design files
comp -include $DSN\src\traffic.v
comp -include "$DSN\src\TestBench\traffic_TB.v"
asim traffic_tb
wave
wave -noreg clk
wave -noreg enable
www.eeworm.com/read/159046/5588570
do fft_32k_wave.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider testbench
add wave -noupdate -format Logic /fft_32K_tb/clk
add wave -noupdate -format Logic /fft_32K_tb/reset
add wa
www.eeworm.com/read/368409/9697018
tf ram16x8d_tb.tf
module testbench();
// Inputs
reg clk;
reg we;
reg [3:0] ADDR;
reg [3:0] DPR_ADDR;
reg [7:0] di;
// Outputs
wire [7:0] SP_OUT;
wire [7:0] DP_OUT;
//
www.eeworm.com/read/202701/15375548
vhd test_vdo_adc_dac_tb.vhd
-- VHDL Test Bench Created from source file test_vdo_adc_dac.vhd -- 11:59:25 07/10/2004
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_ve
www.eeworm.com/read/364127/9921604
v seq4_tb.v
//----- Testbench -----
// Timescale: one time unit = 1ns (e.g., delay specification of #42 means 42ns of time), and
// simulator resolution is 0.1 ns
`timescale 1ns / 100ps
module Counter4_TE
www.eeworm.com/read/447996/7542404
vhw tst_alu_2bit.vhw
-- G:\VIJAY_FPGA_LAB\ALU_2BIT
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Mar 09 14:22:39 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Te
www.eeworm.com/read/447996/7542460
vhw alu_2bit.vhw
-- G:\VIJAY_FPGA_LAB\ALU_2BIT
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sat Feb 18 09:35:47 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Te
www.eeworm.com/read/436679/7766196
vhd tb_romnco.vhd
-- Testbench for CodicNCO
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_RomNCO is
end entity tb_RomNCO;
architecture
www.eeworm.com/read/492009/6429765
tf stopwatch_tb_timing.tf
`timescale 1ns/1ns
module testbench;
reg CLK;
reg RESET;
reg STRTSTOP;
reg GSR;
wire [9:0] TENTHSOUT;
wire [6:0] ONESOUT;
wire [6:0] TENSOUT;
stopwatch UUT (
.CLK(CLK),
.RESET(RESET),
www.eeworm.com/read/408799/11369591
tf stopwatch_tb_timing.tf
`timescale 1ns/1ns
module testbench;
reg CLK;
reg RESET;
reg STRTSTOP;
reg GSR;
wire [9:0] TENTHSOUT;
wire [6:0] ONESOUT;
wire [6:0] TENSOUT;
stopwatch UUT (
.CLK(CLK),
.RESET(RESET),