📄 alu_2bit.vhw
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-- G:\VIJAY_FPGA_LAB\ALU_2BIT
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sat Feb 18 09:35:47 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
--
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;LIBRARY UNISIM;USE UNISIM.VCOMPONENTS.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY alu_2bit IS
END alu_2bit;
ARCHITECTURE testbench_arch OF alu_2bit IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
COMPONENT alu_2bit
PORT (
dis_out : Out std_logic_vector (7 DOWNTO 0);
ain : In std_logic_vector (1 DOWNTO 0);
bin : In std_logic_vector (1 DOWNTO 0);
sout : Out std_logic_vector (1 DOWNTO 0);
sel : In std_logic;
m : In std_logic;
clk1 : In std_logic;
cin : In std_logic;
cout : Out std_logic;
oen1 : Out std_logic;
ce : In std_logic;
oen2 : Out std_logic;
oen3 : Out std_logic;
oen4 : Out std_logic
);
END COMPONENT;
SIGNAL dis_out : std_logic_vector (7 DOWNTO 0);
SIGNAL ain : std_logic_vector (1 DOWNTO 0);
SIGNAL bin : std_logic_vector (1 DOWNTO 0);
SIGNAL sout : std_logic_vector (1 DOWNTO 0);
SIGNAL sel : std_logic;
SIGNAL m : std_logic;
SIGNAL clk1 : std_logic;
SIGNAL cin : std_logic;
SIGNAL cout : std_logic;
SIGNAL oen1 : std_logic;
SIGNAL ce : std_logic;
SIGNAL oen2 : std_logic;
SIGNAL oen3 : std_logic;
SIGNAL oen4 : std_logic;
BEGIN
UUT : alu_2bit
PORT MAP (
dis_out => dis_out,
ain => ain,
bin => bin,
sout => sout,
sel => sel,
m => m,
clk1 => clk1,
cin => cin,
cout => cout,
oen1 => oen1,
ce => ce,
oen2 => oen2,
oen3 => oen3,
oen4 => oen4
);
PROCESS -- clock process for clk1,
BEGIN
CLOCK_LOOP : LOOP
clk1 <= transport '0';
WAIT FOR 20 us;
clk1 <= transport '1';
WAIT FOR 20 us;
WAIT FOR 80 us;
clk1 <= transport '0';
WAIT FOR 80 us;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS -- Process for clk1
VARIABLE TX_OUT : LINE;
VARIABLE TX_ERROR : INTEGER := 0;
PROCEDURE CHECK_dis_out(
next_dis_out : std_logic_vector (7 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (dis_out /= next_dis_out) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("us dis_out="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, dis_out);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_dis_out);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_sout(
next_sout : std_logic_vector (1 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (sout /= next_sout) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("us sout="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, sout);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_sout);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_cout(
next_cout : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (cout /= next_cout) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("us cout="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, cout);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_cout);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_oen1(
next_oen1 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (oen1 /= next_oen1) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("us oen1="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, oen1);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_oen1);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_oen2(
next_oen2 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (oen2 /= next_oen2) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("us oen2="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, oen2);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_oen2);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_oen3(
next_oen3 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (oen3 /= next_oen3) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("us oen3="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, oen3);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_oen3);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_oen4(
next_oen4 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (oen4 /= next_oen4) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("us oen4="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, oen4);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_oen4);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- --------------------
ain <= transport std_logic_vector'("00"); --0
bin <= transport std_logic_vector'("00"); --0
sel <= transport '0';
m <= transport '0';
cin <= transport '0';
ce <= transport '0';
-- --------------------
WAIT FOR 200 us; -- Time=200 us
ain <= transport std_logic_vector'("01"); --1
bin <= transport std_logic_vector'("01"); --1
m <= transport '1';
-- --------------------
WAIT FOR 200 us; -- Time=400 us
ain <= transport std_logic_vector'("00"); --0
bin <= transport std_logic_vector'("01"); --1
-- --------------------
WAIT FOR 200 us; -- Time=600 us
ain <= transport std_logic_vector'("01"); --1
bin <= transport std_logic_vector'("00"); --0
-- --------------------
WAIT FOR 200 us; -- Time=800 us
m <= transport '0';
-- --------------------
WAIT FOR 320 us; -- Time=1120 us
-- --------------------
IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems detected. "
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT, string'(
" errors found in simulation"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;
END testbench_arch;
CONFIGURATION alu_2bit_cfg OF alu_2bit IS
FOR testbench_arch
END FOR;
END alu_2bit_cfg;
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