test_vdo_adc_dac_tb.vhd

hese files are for testing the Video ADC (TLV5734) and DAC THS8133 (DAC0). The ADC and DAC are te

-- VHDL Test Bench Created from source file test_vdo_adc_dac.vhd -- 11:59:25 07/10/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY test_vdo_adc_dac_tb IS
END test_vdo_adc_dac_tb;

ARCHITECTURE behavior OF test_vdo_adc_dac_tb IS 

	COMPONENT test_vdo_adc_dac
	PORT(
		clk : IN std_logic;
		reset : IN std_logic;
		Aout_ADC : IN std_logic_vector(7 downto 0);
		Bout_ADC : IN std_logic_vector(7 downto 0);
		Cout_ADC : IN std_logic_vector(7 downto 0);          
		Mode0_ADC : OUT std_logic;
		Mode1_ADC : OUT std_logic;
		Adc_clk : OUT std_logic;
		Init : OUT std_logic;
		Ext_clp : OUT std_logic;
		G_Y : OUT std_logic;
		Ain_DAC : OUT std_logic_vector(9 downto 0);
		Bin_DAC : OUT std_logic_vector(9 downto 0);
		Cin_DAC : OUT std_logic_vector(9 downto 0);
		Dac_clk : OUT std_logic;
		Blank_DAC : OUT std_logic;
		Sync_DAC : OUT std_logic;
		Sync_T : OUT std_logic;
		Mode1_DAC : OUT std_logic;
		Mode2_DAC : OUT std_logic
		);
	END COMPONENT;

	SIGNAL clk :  std_logic := '0';
	SIGNAL reset :  std_logic := '0';
	SIGNAL Aout_ADC :  std_logic_vector(7 downto 0):= (others => '0');
	SIGNAL Bout_ADC :  std_logic_vector(7 downto 0):= (others => '0');
	SIGNAL Cout_ADC :  std_logic_vector(7 downto 0):= (others => '0');
	SIGNAL Mode0_ADC :  std_logic;
	SIGNAL Mode1_ADC :  std_logic;
	SIGNAL Adc_clk :  std_logic;
	SIGNAL Init :  std_logic;
	SIGNAL Ext_clp :  std_logic;
	SIGNAL G_Y :  std_logic;
	SIGNAL Ain_DAC :  std_logic_vector(9 downto 0);
	SIGNAL Bin_DAC :  std_logic_vector(9 downto 0);
	SIGNAL Cin_DAC :  std_logic_vector(9 downto 0);
	SIGNAL Dac_clk :  std_logic;
	SIGNAL Blank_DAC :  std_logic;
	SIGNAL Sync_DAC :  std_logic;
	SIGNAL Sync_T :  std_logic;
	SIGNAL Mode1_DAC :  std_logic;
	SIGNAL Mode2_DAC :  std_logic;

BEGIN

	uut: test_vdo_adc_dac PORT MAP(
		clk => clk,
		reset => reset,
		Aout_ADC => Aout_ADC,
		Bout_ADC => Bout_ADC,
		Cout_ADC => Cout_ADC,
		Mode0_ADC => Mode0_ADC,
		Mode1_ADC => Mode1_ADC,
		Adc_clk => Adc_clk,
		Init => Init,
		Ext_clp => Ext_clp,
		G_Y => G_Y,
		Ain_DAC => Ain_DAC,
		Bin_DAC => Bin_DAC,
		Cin_DAC => Cin_DAC,
		Dac_clk => Dac_clk,
		Blank_DAC => Blank_DAC,
		Sync_DAC => Sync_DAC,
		Sync_T => Sync_T,
		Mode1_DAC => Mode1_DAC,
		Mode2_DAC => Mode2_DAC
	);


-- *** Test Bench - User Defined Section ***
	reset <= '1', '0' after 153 ns ;

	clk <= not clk after 16 ns ;

	Aout_ADC <= x"55" after 250 ns ;
	Bout_ADC <= x"35" after 250 ns ;
	Cout_ADC <= x"85" after 250 ns ;

-- *** End Test Bench - User Defined Section ***

END;