代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/247536/4481533
cpp xsimtestbench_arch.cpp
#include "work/scramblerwave/testbench_arch.h"
static const char * HSimCopyRightNotice = "Copyright 2004-2005, Xilinx Inc. All rights reserved.";
#include "F:/Xilinx/vhdl/hdp/ieee/std_logic_1164/std
www.eeworm.com/read/310565/3695593
vhd 56_vhdl.vhd
-- Author : yzf
-- Created On: Tue Dec 12 08:26:19 1995
-- Testbench for prefetch.prefetch
library STD;
library WORK;
use STD.STANDARD.ALL;
use WORK.ALL;
entity test_prefetch is
end t
www.eeworm.com/read/439207/1807104
vhd 56_vhdl.vhd
-- Author : yzf
-- Created On: Tue Dec 12 08:26:19 1995
-- Testbench for prefetch.prefetch
library STD;
library WORK;
use STD.STANDARD.ALL;
use WORK.ALL;
entity test_prefetch is
end t
www.eeworm.com/read/368409/9697001
tf mul3_1_casz_tb.tf
module testbench();
// Inputs
reg [2:0] sel;
reg [3:0] a;
reg [3:0] b;
reg [3:0] c;
// Outputs
wire [3:0] y;
// Instantiate the UUT
mul3_1_casez uut (.y(y)
www.eeworm.com/read/368409/9697020
tf reg4_nbp_tb.tf
module testbench();
// DATE: Thu May 01 10:38:03 2003
// TITLE:
// MODULE: reg4_bpa
// DESIGN: reg4_bpa
// FILENAME: reg4_bpa
// PROJECT: reg4
// VERSION: Version 1.0
www.eeworm.com/read/368409/9697025
tf mut4_2_1tb.tf
module testbench();
// Inputs
reg s;
reg [3:0] a;
reg [3:0] b;
// Outputs
wire [3:0] y;
// Instantiate the UUT
mul4_2_1 mul4_2_1tb (
.y(y),
.s(
www.eeworm.com/read/368409/9697038
tf reg4_bpa_tb.tf
module testbench();
// DATE: Thu May 01 10:38:03 2003
// TITLE:
// MODULE: reg4_bpa
// DESIGN: reg4_bpa
// FILENAME: reg4_bpa
// PROJECT: reg4
// VERSION: Version 1.0
www.eeworm.com/read/168700/9901584
timesim_vhw t_compact.timesim_vhw
-- D:\FPGA\仿真\DIVIDER_定点除法器
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Jul 13 10:54:53 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test
www.eeworm.com/read/168700/9901715
timesim_vhw t_divider.timesim_vhw
-- D:\FPGA\仿真\DIVIDER_定点除法器
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Jul 13 10:58:04 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test
www.eeworm.com/read/168700/9901719
vhw t_divider.vhw
-- D:\FPGA\仿真\DIVIDER_定点除法器
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Jul 13 10:59:57 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test