mut4_2_1tb.tf

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

module testbench();


// Inputs
    reg s;
    reg [3:0] a;
    reg [3:0] b;


// Outputs
    wire [3:0] y;

// Instantiate the UUT
    mul4_2_1 mul4_2_1tb (
        .y(y), 
        .s(s), 
        .a(a), 
        .b(b)
        );


// Initialize Inputs
initial $monitor($time, "s = %b,  a = %b,  b = %b", s, a, b);

initial begin
  s = 0;
  a = 4'b0000;
  b = 4'b1111;
end                  //Initialize s, a, and b

always #10 s = ~s;	 //set s with a period 20 units

initial begin
  #20 a = 4'b0011;
  #20 b = 4'b0101;
  #50 a = 4'b1100;
  #50 b = 4'b1010;
end

initial #200 $finish; //Complete simulation after 400 units
endmodule