mul3_1_casz_tb.tf

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

module testbench();
// Inputs
    reg [2:0] sel;
    reg [3:0] a;
    reg [3:0] b;
    reg [3:0] c;


// Outputs
    wire [3:0] y;

// Instantiate the UUT
    mul3_1_casez uut (.y(y), .sel(sel), .a(a), .b(b), .c(c));


 
// Montoring signals
initial $monitor($time, "y=%h, sel=%b, a=%h, b=%h, c=%h", y, sel, a, b, c);

// Initialize Inputs
initial begin
  sel = 4'b0000;
  a = 4'b0000;
  b = 4'b1010;
  c = 4'b1111;
end  

always
  #10 sel = sel + 4'h1;

 initial #80 $finish; //Complete simulation after 160 units

endmodule