代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/391802/8376809
vhd 63_stim.vhd
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
--Notice:
--This file has been modified by Wu Qing-ping on Apr 23, 1998.
--Modification: I change a
www.eeworm.com/read/384728/8848668
vhd 63_stim.vhd
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
--Notice:
--This file has been modified by Wu Qing-ping on Apr 23, 1998.
--Modification: I change a
www.eeworm.com/read/284185/8955317
vhd 63_stim.vhd
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
--Notice:
--This file has been modified by Wu Qing-ping on Apr 23, 1998.
--Modification: I change a
www.eeworm.com/read/382142/9046334
vhd micro_master_tb.vhd
-- micro_master_tb.vhd
--
-- Created: 6/17/99 ALS
-- This file emulates the uC that interfaces to the I2C design. This testbench
-- will interface to one I2C post-layout design and configure this
www.eeworm.com/read/170129/9818120
vhd addsubtest.vhd
-- VHDL Test Bench Created from source file addsub.vhd -- 11:11:58 06/15/2006
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for t
www.eeworm.com/read/366183/9825706
vhd 63_stim.vhd
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
--Notice:
--This file has been modified by Wu Qing-ping on Apr 23, 1998.
--Modification: I change a
www.eeworm.com/read/360684/10082135
vhd micro_master_tb.vhd
-- micro_master_tb.vhd
--
-- Created: 6/17/99 ALS
-- This file emulates the uC that interfaces to the I2C design. This testbench
-- will interface to one I2C post-layout design and configure this
www.eeworm.com/read/278084/10574989
vhd 63_stim.vhd
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
--Notice:
--This file has been modified by Wu Qing-ping on Apr 23, 1998.
--Modification: I change a
www.eeworm.com/read/349305/10836826
transcript
# Reading D:/Modeltech_6.2b/tcl/vsim/pref.tcl
# OpenFile G:/verilog/SRAMtest/SRAMtest.v
project open G:/verilog/SRAMtest/SRAMtest
# Loading project SRAMtest
# Creating Testbench...
# Adding Fi
www.eeworm.com/read/462927/7191575
v pll_ram_tb.v
//This is a simple modelSim simulation flow demo
//Function: simple testbench of pll_tb.v
//2004-12-2 Westor
`timescale 1ns/100ps
module pll_ram_tb ();
reg clk_in;