transcript

FPGA的SRAM存储器的控制程序

# Reading D:/Modeltech_6.2b/tcl/vsim/pref.tcl 
# OpenFile G:/verilog/SRAMtest/SRAMtest.v 
project open G:/verilog/SRAMtest/SRAMtest
# Loading project SRAMtest
# Creating Testbench... 
# Adding File to Project... 
# Compiling Testbench into library work... 
# Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
# -- Compiling module SRAM_16Bit_512K_tb
# 
# Top level modules:
# 	SRAM_16Bit_512K_tb
# Opening Source file on Testbench... 
# Compile of SRAMtest.v was successful.
# Compile of Reset_Delay.v was successful.
# Compile of SEG7_LUT.v was successful.
# Compile of SEG7_LUT_4.v was successful.
# Compile of SRAM_16Bit_512K.v was successful.
# Compile of SRAM_16Bit_512K_tb.v failed with 1 errors.
# 6 compiles, 1 failed with 1 error. 
# Compile of SRAMtest.v was successful.
# Compile of Reset_Delay.v was successful.
# Compile of SEG7_LUT.v was successful.
# Compile of SEG7_LUT_4.v was successful.
# Compile of SRAM_16Bit_512K.v was successful.
# Compile of SRAM_16Bit_512K_tb.v failed with 1 errors.
# 6 compiles, 1 failed with 1 error. 
# Compile of SRAMtest.v was successful.
# Compile of Reset_Delay.v was successful.
# Compile of SEG7_LUT.v was successful.
# Compile of SEG7_LUT_4.v was successful.
# Compile of SRAM_16Bit_512K.v was successful.
# Compile of SRAM_16Bit_512K_tb.v failed with 1 errors.
# 6 compiles, 1 failed with 1 error. 
# Compile of SRAMtest.v was successful.
# Compile of Reset_Delay.v was successful.
# Compile of SEG7_LUT.v was successful.
# Compile of SEG7_LUT_4.v was successful.
# Compile of SRAM_16Bit_512K.v was successful.
# Compile of SRAM_16Bit_512K_tb.v failed with 1 errors.
# 6 compiles, 1 failed with 1 error. 
# Compile of SRAMtest.v was successful.
# Compile of Reset_Delay.v was successful.
# Compile of SEG7_LUT.v was successful.
# Compile of SEG7_LUT_4.v was successful.
# Compile of SRAM_16Bit_512K.v was successful.
# Compile of SRAM_16Bit_512K_tb.v was successful.
# 6 compiles, 0 failed with no errors. 
vsim work.SRAM_16Bit_512K_tb
# vsim work.SRAM_16Bit_512K_tb 
# Loading work.SRAM_16Bit_512K_tb
# Loading work.SRAM_16Bit_512K
# ** Error: (vsim-3053) SRAM_16Bit_512K_tb.v(34): Illegal output or inout port connection (port 'SRAM_DQ').
#         Region: /SRAM_16Bit_512K_tb/DUT
# Error loading design
vsim work.SRAM_16Bit_512K_tb
# vsim work.SRAM_16Bit_512K_tb 
# Loading work.SRAM_16Bit_512K_tb
# Loading work.SRAM_16Bit_512K
# ** Error: (vsim-3053) SRAM_16Bit_512K_tb.v(34): Illegal output or inout port connection (port 'SRAM_DQ').
#         Region: /SRAM_16Bit_512K_tb/DUT
# Error loading design
# Compile of SRAMtest.v was successful.
# Compile of Reset_Delay.v was successful.
# Compile of SEG7_LUT.v was successful.
# Compile of SEG7_LUT_4.v was successful.
# Compile of SRAM_16Bit_512K.v was successful.
# Compile of SRAM_16Bit_512K_tb.v was successful.
# 6 compiles, 0 failed with no errors. 
vsim work.SRAM_16Bit_512K_tb
# vsim work.SRAM_16Bit_512K_tb 
# Loading work.SRAM_16Bit_512K_tb
# Loading work.SRAM_16Bit_512K
# ** Error: (vsim-3053) SRAM_16Bit_512K_tb.v(34): Illegal output or inout port connection (port 'SRAM_DQ').
#         Region: /SRAM_16Bit_512K_tb/DUT
# Error loading design
# Compile of SRAMtest.v was successful.
# Compile of Reset_Delay.v was successful.
# Compile of SEG7_LUT.v was successful.
# Compile of SEG7_LUT_4.v was successful.
# Compile of SRAM_16Bit_512K.v was successful.
# Compile of SRAM_16Bit_512K_tb.v was successful.
# 6 compiles, 0 failed with no errors. 
vsim work.SRAM_16Bit_512K_tb
# vsim work.SRAM_16Bit_512K_tb 
# Loading work.SRAM_16Bit_512K_tb
# Loading work.SRAM_16Bit_512K
add wave sim:/SRAM_16Bit_512K_tb/*
run -all
# Break in Module SRAM_16Bit_512K_tb at SRAM_16Bit_512K_tb.v line 48
quit -sim
# reading D:\Modeltech_6.2b\win32/../modelsim.ini
# Loading project de2_SRAM
# Compile of SRAM_2.v failed with 1 errors.
# Compile of CLK_10MHZ.v was successful.
# 2 compiles, 1 failed with 1 error. 
# Compile of SRAM_2.v failed with 1 errors.
# Compile of CLK_10MHZ.v was successful.
# 2 compiles, 1 failed with 1 error. 
# Compile of SRAM_2.v failed with 1 errors.
# Compile of CLK_10MHZ.v was successful.
# 2 compiles, 1 failed with 1 error. 
# Compile of SRAM_2.v failed with 1 errors.
# Compile of CLK_10MHZ.v was successful.
# 2 compiles, 1 failed with 1 error. 
# Error: 揪肺