代码搜索：testbench

找到约 2,392 项符合「testbench」的源代码

代码结果 2,392
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/153614/12021079

vhd 56_stim.vhd

-- Author : yzf -- Created On: Tue Dec 12 08:26:19 1995 -- Testbench for prefetch.prefetch use work.types.all; architecture BENCH of test_prefetch is component prefetch PORT( BR
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www.eeworm.com/read/151305/12220521

vhd 56_stim.vhd

-- Author : yzf -- Created On: Tue Dec 12 08:26:19 1995 -- Testbench for prefetch.prefetch use work.types.all; architecture BENCH of test_prefetch is component prefetch PORT( BR
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www.eeworm.com/read/149028/12408348

vhd 56_stim.vhd

-- Author : yzf -- Created On: Tue Dec 12 08:26:19 1995 -- Testbench for prefetch.prefetch use work.types.all; architecture BENCH of test_prefetch is component prefetch PORT( BR
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www.eeworm.com/read/215971/15031612

vhd fifoctlr_cc_tb.vhd

-- N:\DATA\EXAMPLES\FIFO_VHD_131 -- VHDL Test Bench created by HDL Bencher -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Bench Waveform -- 2) To use th
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www.eeworm.com/read/212004/15168497

bat createlib.bat

vlib work vlib cpu vmap cpu cpu @echo Compile Altera mf library @echo Only required for the testbench memories vlib altera_mf @echo !!!Change the path below to point to the quartus installation
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www.eeworm.com/read/17937/767653

tf adder8_for_tb.tf

module testbench(); // Inputs reg [7:0] a; reg [7:0] b; reg cin; // Outputs wire [7:0] sum; wire cout; // Instantiate the UUT adder8_for uut (.sum(sum), .c
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www.eeworm.com/read/17937/767662

tf shl4_for_tb.tf

module testbench(); // Inputs reg CLK; reg RESET; reg Din; // Outputs wire [3:0] Q; // Instantiate the UUT shl4_for uut (.Q(Q), .CLK(CLK), .RESET(RESET), .Din(D
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www.eeworm.com/read/17937/767683

tf encod8_3_casex_tb.tf

module testbench(); // Inputs reg [7:0] i; // Outputs wire [2:0] y; // Instantiate the UUT encod8_3_casex uut (.y(y), .i(i)); // Initialize Inputs initial $monit
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www.eeworm.com/read/17937/767692

tf repeat_tb.tf

module testbench(); reg [7:0] Din; // Inputs wire [3:0] ones;// Outputs repeat_1s uut (.ones(ones), .Din(Din));// Instantiate the UUT // Initialize Inputs initial $monitor ($time,
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www.eeworm.com/read/32453/1034251

100vhdl+

-- Author : yzf -- Created On: Tue Dec 12 08:26:19 1995 -- Testbench for prefetch.prefetch use work.types.all; architecture BENCH of test_prefetch is component prefetch PORT( BR
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