56_stim.vhd

来自「北京里工大学ASIC设计研究所的100个 VHDL程序设计例子」· VHDL 代码 · 共 69 行

-- Author    : yzf
-- Created On: Tue Dec 12 08:26:19 1995
-- Testbench for prefetch.prefetch

use work.types.all;

architecture BENCH of test_prefetch is 
	component prefetch
	    PORT(
		BRANCHPC: IN SHORT;
		IBUS: IN SHORT;
		BRANCH: IN BIT;
		IRE: IN BIT;
		PPC: OUT SHORT;
		POPC: OUT SHORT;
		OBUS: OUT SHORT
	    );
	end component;

	signal BRANCHPC:SHORT;
	signal IBUS:SHORT;
	signal BRANCH:BIT;
	signal IRE:BIT;
	signal PPC:SHORT;
	signal POPC:SHORT;
	signal OBUS:SHORT;

for all: prefetch use entity work.prefetch;

begin
	prefetch_I1: prefetch 
	    port map (
		BRANCHPC => BRANCHPC,
		IBUS => IBUS,
		BRANCH => BRANCH,
		IRE => IRE,
		PPC => PPC,
		POPC => POPC,
		OBUS => OBUS
	    );

	prefetch_driver: process
	begin
		wait for 10 ns;
		ibus <= 0;
		branch <= '0';

		wait for 50 ns;
		ibus <= 10;
		branch <= '1';

		wait for 50 ns;
		ibus <= 14;
		branch <= '0';

		wait for 50 ns;
		ibus <= 24;
		branch <= '1';

		wait for 50 ns;
		assert false
		report "---End of Simulation---"
		severity error;

	end process;

	IRE <= not IRE after 50 ns;
END BENCH;