fifoctlr_cc_tb.vhd

fifo vhdl源程序

-- N:\DATA\EXAMPLES\FIFO_VHD_131
-- VHDL Test Bench created by	HDL Bencher 
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY  ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

LIBRARY  unisim;
USE unisim.Vcomponents.all;

LIBRARY ieee;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY tb_cc IS
END tb_cc;

ARCHITECTURE tb_cc_arch OF tb_cc IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT fifoctlr_cc
		PORT (
			clock_in : IN  std_logic;
			read_enable_in : IN  std_logic;
			write_enable_in : IN  std_logic;
			write_data_in : IN  std_logic_vector (7 DOWNTO 0);
			fifo_gsr_in : IN  std_logic;
			read_data_out : OUT  std_logic_vector (7 DOWNTO 0);
			full_out : OUT  std_logic;
			empty_out : OUT  std_logic;
			fifocount_out : OUT  std_logic_vector (3 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL clock_in : std_logic;
	SIGNAL read_enable_in : std_logic;
	SIGNAL write_enable_in : std_logic;
	SIGNAL write_data_in : std_logic_vector (7 DOWNTO 0);
	SIGNAL fifo_gsr_in : std_logic;
	SIGNAL read_data_out : std_logic_vector (7 DOWNTO 0);
	SIGNAL full_out : std_logic;
	SIGNAL empty_out : std_logic;
	SIGNAL fifocount_out : std_logic_vector (3 DOWNTO 0);

BEGIN
	UUT : fifoctlr_cc
	PORT MAP (
		clock_in => clock_in,
		read_enable_in => read_enable_in,
		write_enable_in => write_enable_in,
		write_data_in => write_data_in,
		fifo_gsr_in => fifo_gsr_in,
		read_data_out => read_data_out,
		full_out => full_out,
		empty_out => empty_out,
		fifocount_out => fifocount_out
	);

	PROCESS -- clock process for clock_in,
	BEGIN
		CLOCK_LOOP : LOOP
		clock_in <= transport '0';
		WAIT FOR 15 ns;
		clock_in <= transport '1';
		WAIT FOR 18 ns;
		WAIT FOR 7 ns;
		clock_in <= transport '0';
		WAIT FOR 10 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clock_in
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_read_data_out(
			next_read_data_out : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (read_data_out /= next_read_data_out) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns read_data_out="));
				write(TX_LOC, read_data_out);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_read_data_out);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_full_out(
			next_full_out : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (full_out /= next_full_out) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns full_out="));
				write(TX_LOC, full_out);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_full_out);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_empty_out(
			next_empty_out : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (empty_out /= next_empty_out) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns empty_out="));
				write(TX_LOC, empty_out);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_empty_out);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_fifocount_out(
			next_fifocount_out : std_logic_vector (3 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (fifocount_out /= next_fifocount_out) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns fifocount_out="));
				write(TX_LOC, fifocount_out);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_fifocount_out);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		read_enable_in <= transport '0';
		write_enable_in <= transport '0';
		write_data_in <= transport std_logic_vector'("00000000"); --0
		fifo_gsr_in <= transport '1';
		-- --------------------
		WAIT FOR 150 ns; -- Time=150 ns
		fifo_gsr_in <= transport '0';
		-- --------------------
		WAIT FOR 50 ns; -- Time=200 ns
		write_enable_in <= transport '1';
		write_data_in <= transport std_logic_vector'("00000000"); --0
		fifo_gsr_in <= transport '0';
		-- --------------------
		WAIT FOR 50 ns; -- Time=250 ns
		write_enable_in <= transport '1';
		write_data_in <= transport std_logic_vector'("00000001"); --1
		fifo_gsr_in <= transport '0';
		-- --------------------
		WAIT FOR 50 ns; -- Time=300 ns
		write_data_in <= transport std_logic_vector'("00000010"); --2
		-- --------------------
		WAIT FOR 50 ns; -- Time=350 ns
		write_data_in <= transport std_logic_vector'("00000011"); --3
		-- --------------------
		WAIT FOR 50 ns; -- Time=400 ns
		write_data_in <= transport std_logic_vector'("00000100"); --4
		-- --------------------
		WAIT FOR 50 ns; -- Time=450 ns
		write_data_in <= transport std_logic_vector'("00000101"); --5
		fifo_gsr_in <= transport '1';
		-- --------------------
		WAIT FOR 50 ns; -- Time=500 ns
		write_data_in <= transport std_logic_vector'("00000110"); --6
		-- --------------------
		WAIT FOR 50 ns; -- Time=550 ns
		write_data_in <= transport std_logic_vector'("00000111"); --7
		-- --------------------
		WAIT FOR 50 ns; -- Time=600 ns
		write_data_in <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 50 ns; -- Time=650 ns
		write_data_in <= transport std_logic_vector'("00001001"); --9
		-- --------------------
		WAIT FOR 50 ns; -- Time=700 ns
		write_data_in <= transport std_logic_vector'("00001010"); --A
		-- --------------------
		WAIT FOR 50 ns; -- Time=750 ns
		write_data_in <= transport std_logic_vector'("00001011"); --B
		-- --------------------
		WAIT FOR 50 ns; -- Time=800 ns
		write_data_in <= transport std_logic_vector'("00001100"); --C
		-- --------------------
		WAIT FOR 50 ns; -- Time=850 ns
		write_data_in <= transport std_logic_vector'("00001101"); --D
		-- --------------------
		WAIT FOR 50 ns; -- Time=900 ns
		write_data_in <= transport std_logic_vector'("00001110"); --E
		-- --------------------
		WAIT FOR 50 ns; -- Time=950 ns
		write_data_in <= transport std_logic_vector'("00001111"); --F
		-- --------------------
		WAIT FOR 50 ns; -- Time=1000 ns
		write_data_in <= transport std_logic_vector'("00010000"); --10
		-- --------------------
		WAIT FOR 50 ns; -- Time=1050 ns
		write_data_in <= transport std_logic_vector'("00010001"); --11
		-- --------------------
		WAIT FOR 50 ns; -- Time=1100 ns
		write_data_in <= transport std_logic_vector'("00010010"); --12
		-- --------------------
		WAIT FOR 50 ns; -- Time=1150 ns
		write_data_in <= transport std_logic_vector'("00010011"); --13
		fifo_gsr_in <= transport '0';
		-- --------------------
		WAIT FOR 50 ns; -- Time=1200 ns
		read_enable_in <= transport '1';
		write_enable_in <= transport '0';
		-- --------------------
		WAIT FOR 1290 ns; -- Time=2490 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			write(TX_OUT,string'("No errors or warnings"));
			writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			write(TX_OUT, TX_ERROR);
			write(TX_OUT, string'(
				" errors found in simulation"));
			writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END tb_cc_arch;

CONFIGURATION fifoctlr_cc_cfg OF tb_cc IS
	FOR tb_cc_arch
	END FOR;
END fifoctlr_cc_cfg;